#ifndef _DMCINIT_HH__
#define _DMCINIT_HH__
#ifdef __cplusplus
extern "C" {
#endif


/*****************************************DMC_CTL**********************************************/
/* ! enable DDR3 controller */
#define CFG0_BIT_DMC_CTL_DDR3EN                     1ul
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_CTL_RDTOWR                     5ul

#define CFG0_REG_DMC_CTL_VALUE      ((CFG0_BIT_DMC_CTL_DDR3EN<<BITP_DMC_CTL_DDR3EN)|(BITM_DMC_CTL_INIT)|(CFG0_BIT_DMC_CTL_RDTOWR<<BITP_DMC_CTL_RDTOWR))

/***************************************** DMC  CFG**********************************************/
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_CFG_IFWID                      (ENUM_DMC_CFG_IFWID16)
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_CFG_SDRWID                     (ENUM_DMC_CFG_SDRWID16)
/*! DDR3 memory size*/
#define CFG0_BIT_DMC_CFG_SDRSIZE                    (ENUM_DMC_CFG_SDRSIZE8G)
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_CFG_EXTBANK                    0ul

#define CFG0_REG_DMC_CFG_VALUE      ((CFG0_BIT_DMC_CFG_IFWID)|(CFG0_BIT_DMC_CFG_SDRWID)|(CFG0_BIT_DMC_CFG_SDRSIZE)|(CFG0_BIT_DMC_CFG_EXTBANK    <<BITP_DMC_CFG_EXTBANK))

/*****************************************DMC_TR0**********************************************/
/*! Trcd value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TRCD                       7ul
/*! Twtr value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TWTR                       5ul
/*! Trp value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TRP                        7ul
/*! Tras value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TRAS                       20ul
/*! Trc value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TRC                        27ul
/*! Tmrd value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR0_TMRD                       4ul

#define CFG0_REG_DMC_TR0_VALUE      ((CFG0_BIT_DMC_TR0_TRCD<<BITP_DMC_TR0_TRCD)|(CFG0_BIT_DMC_TR0_TWTR<<BITP_DMC_TR0_TWTR)|(CFG0_BIT_DMC_TR0_TRP<<BITP_DMC_TR0_TRP)|(CFG0_BIT_DMC_TR0_TRAS<<BITP_DMC_TR0_TRAS)|(CFG0_BIT_DMC_TR0_TRC<<BITP_DMC_TR0_TRC)|(CFG0_BIT_DMC_TR0_TMRD<<BITP_DMC_TR0_TMRD))

/*****************************************DMC_TR1**********************************************/
/*! Tref value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR1_TREF                        4160ul
/*! Trfc value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR1_TRFC                        187ul
/*! Trrd value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR1_TRRD                        6ul

#define CFG0_REG_DMC_TR1_VALUE      ((CFG0_BIT_DMC_TR1_TREF<<BITP_DMC_TR1_TREF)|(CFG0_BIT_DMC_TR1_TRFC<<BITP_DMC_TR1_TRFC)|(CFG0_BIT_DMC_TR1_TRRD<<BITP_DMC_TR1_TRRD))

/*****************************************DMC_TR2**********************************************/

/*! Tfaw value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR2_TFAW                          27ul
/*! Trtp value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR2_TRTP                          5ul
/*! Twr value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR2_TWR                           8ul
/*! Txp value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR2_TXP                           4ul
/*! Tcke value in DDR clock cycles*/
#define CFG0_BIT_DMC_TR2_TCKE                          3ul

#define CFG0_REG_DMC_TR2_VALUE      ((CFG0_BIT_DMC_TR2_TFAW<<BITP_DMC_TR2_TFAW)|(CFG0_BIT_DMC_TR2_TRTP<<BITP_DMC_TR2_TRTP)|(CFG0_BIT_DMC_TR2_TWR<<BITP_DMC_TR2_TWR)|(CFG0_BIT_DMC_TR2_TXP<<BITP_DMC_TR2_TXP)|(CFG0_BIT_DMC_TR2_TCKE<<BITP_DMC_TR2_TCKE))

/****************************************DMC  DLLCTLCFG**********************************************/




#define ADI_DMC_PARAM_DLLCOUNT                         247ul

/*! ceil ( 15ns/DDRclock in Hz)  */
#define CFG0_REG_DMC_DATACYC                          8ul

#define CFG0_REG_DDR_DLLCTLCFG      ((((CFG0_REG_DMC_DATACYC  << BITP_DMC_DLLCTL_DATACYC) | (ADI_DMC_PARAM_DLLCOUNT<<BITP_DMC_DLLCTL_DLLCALRDCNT))<<16)|(CFG0_BIT_DMC_CFG_IFWID) |CFG0_BIT_DMC_CFG_SDRWID |  CFG0_BIT_DMC_CFG_SDRSIZE)
/****************************************DMC  MR0**********************************************/

/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_MR0_BLEN                           0ul
/*! CAS Read latency bit 0 value*/
#define CFG0_BIT_DMC_MR0_CL0                            0ul
/*! CAS Read latency [2:1] bits*/
#define CFG0_BIT_DMC_MR0_CL                             3ul
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_MR0_DLLRST                         1ul
/*! Write recovery value*/
#define CFG0_BIT_DMC_MR0_WRRECOV                        4ul

#define CFG0_REG_DMC_MR0_VALUE             ((CFG0_BIT_DMC_MR0_BLEN<<BITP_DMC_MR_BLEN)|(CFG0_BIT_DMC_MR0_CL0<<BITP_DMC_MR_CL0)|(CFG0_BIT_DMC_MR0_CL<<BITP_DMC_MR_CL)|(CFG0_BIT_DMC_MR0_DLLRST<<BITP_DMC_MR_DLLRST)|(CFG0_BIT_DMC_MR0_WRRECOV<<BITP_DMC_MR_WRRECOV))

/****************************************DMC  MR1**********************************************/
/*! Constant value, should not be altered*/
#define CFG0_BIT_DMC_MR1_DLLEN                            0ul
/*! Bit 0 of the output DS*/
#define CFG0_BIT_DMC_MR1_DIC0                             0ul
/*! Bit 0 of the ODT*/
#define CFG0_BIT_DMC_MR1_RTT0                             1ul
/*! Additive latency setting*/
#define CFG0_BIT_DMC_MR1_AL                               1ul
/*! Bit 1 of the output DS*/
#define CFG0_BIT_DMC_MR1_DIC1                             0ul
/*! Bit 1 of the ODT*/
#define CFG0_BIT_DMC_MR1_RTT1                             0ul
/*! Bit 2 of the ODT*/
#define CFG0_BIT_DMC_MR1_RTT2                             0ul
#define CFG0_BIT_DMC_MR1_TDQS                             0ul
#define CFG0_BIT_DMC_MR1_QOFF                             0ul

#define CFG0_REG_DMC_MR1_VALUE       ((CFG0_BIT_DMC_MR1_DLLEN<<BITP_DMC_MR1_DLLEN)|(CFG0_BIT_DMC_MR1_DIC0<<BITP_DMC_MR1_DIC0)|(CFG0_BIT_DMC_MR1_RTT0<<BITP_DMC_MR1_RTT0)|(CFG0_BIT_DMC_MR1_AL<<BITP_DMC_MR1_AL)|(CFG0_BIT_DMC_MR1_DIC1<<BITP_DMC_MR1_DIC1)|(CFG0_BIT_DMC_MR1_RTT1<<BITP_DMC_MR1_RTT1)|(CFG0_BIT_DMC_MR1_RTT2<<BITP_DMC_MR1_RTT2)|(CFG0_BIT_DMC_MR1_TDQS<<BITP_DMC_MR1_TDQS)|(CFG0_BIT_DMC_MR1_QOFF<<BITP_DMC_MR1_QOFF))

/**************************************** DMC  MR2MR3**********************************************/
/*! CAS write latency*/
#define CFG0_BIT_DMC_MR2_CWL                              1ul
#define CFG0_REG_DMC_MR2MR3      (((CFG0_BIT_DMC_MR2_CWL<<BITP_DMC_MR2_CWL))<<16)

#define CFG0_REG_DMC_MRMR1        (CFG0_REG_DMC_MR1_VALUE|(CFG0_REG_DMC_MR0_VALUE<<16ul))

/*! Core clock and DCLK ratio*/
#define csel_dsel_r                                       10ul



#define TrigCalib 0ul
#define DelayTrim 0ul
#define DqsTrim  0ul
#define ClkTrim 0ul
#define CLKDIR 0ul
#define Bypasscode 0ul
#define Dqscode 0ul
#define Clkcode 0ul
#define OfstdCycle 2ul


/* including missing declarations*/
#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL    (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Reset the Lane DLL */
#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL    (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Reset the Lane DLL */
#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Compute Datacycle */
#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Compute Datacycle */
#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT    (_ADI_MSK_3(0x08000000,0x08000000UL, uint32_t  ))    /*  Reset the Data Pads */
#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT    (_ADI_MSK_3(0x08000000,0x08000000UL, uint32_t  ))    /*  Reset the Data Pads */
#define BITP_DMC_CTL_RDTOWR                   9            /*  Read-to-Write Cycle */
#define BITP_DMC_TR2_TWR                     12            /*  Timing Write Recovery */



typedef enum
{
  ADI_DMC_SUCCESS=0u,
  ADI_DMC_FAILURE
}ADI_DMC_RESULT;

/* structure which holds DMC register values */
typedef struct
{

  uint32_t ulDDR_DLLCTLCFG;               /*!< Content of DDR DLLCTL and DMC_CFG register     */
  uint32_t ulDDR_EMR2EMR3;                /*!< Content of the DDR EMR2 and EMR3 Register      */
  uint32_t ulDDR_CTL;                     /*!< Content of the DDR Control                   */
  uint32_t ulDDR_MREMR1;                  /*!< Content of the DDR MR and EMR1 Register      */
  uint32_t ulDDR_TR0;                     /*!< Content of the DDR Timing Register      */
  uint32_t ulDDR_TR1;                     /*!< Content of the DDR Timing Register      */
  uint32_t ulDDR_TR2;                     /*!< Content of the DDR Timing Register      */
  uint32_t ulDDR_ZQCTL0;                  /*!< Content of ZQCTL0 register */
  uint32_t ulDDR_ZQCTL1;                  /*!< Content of ZQCTL1 register */
  uint32_t ulDDR_ZQCTL2;                  /*!< Content of ZQCTL2 register */

}ADI_DMC_CONFIG;

int dmc_cfg0_init(void);

#ifdef __cplusplus
}
#endif
#endif