/*
 * board.h
 *
 *  Created on: 2021Äê9ÔÂ1ÈÕ
 *      Author: graydon
 */

//#ifndef DRV_BOARD_H_
//#define DRV_BOARD_H_
#pragma once

#ifdef __cplusplus
extern "C" {
#endif

#include "typedefs.h"
#include "sru_dai.h"

extern unsigned int SAMPLE_RATE;
extern unsigned int SAMPLE_NUM;

/*
 * ΪÁ˺Í21489 ±£³Ö¼æÈÝ£¬ ЭÒ鶨ÒåÈ«²¿²ÉÓÃshortÀàÐÍ
 * */

////for dsp-21569 ,sport 0a,0b, sport 1a ,1b, .... ,sport 7a,7b.
////for dsp-21489 ,sport 0,sport 1,...,sport7.
struct SportDef{
	short spid;
	short  enable;
	short  enable_sec;
	short interrupt;

	//clock config.
	short rx; //rx or tx.
	short opmode; //0-tdm ,1 - IIS mode
	short clke; //0-Clock falling edge sample.,1-Clock rising edge sample
	short lfs; //0-active high Frame sync ,1- Active-Low Frame Sync

	short   mfd; //Frame Delay.
	short   slots;
	short   vld; //valid channel.
	short   follow_intr_no;
};

struct LinkPortDef{
	short lpid;//link portË÷Òý£¬ÊÇlink port0»¹ÊÇlink port1
	short enable;//ÊÇ·ñʹÄܸÃlink port
	short interrupt;//ÊÇ·ñʹÓÃÖжÏ
	short rx; //rx or tx.¸Ãlink portµÄ·½Ïò£º1ΪÊÕ£¬0Ϊ·¢
	short follow_intr_no;
	short   slots;//¾ÍÊÇ´ú±íÓм¸¸öͨµÀ
};

//for PCG A B C D.
struct PCGDef{
	short  enable;

	short  opmode ; //0-iis, 1 -tdm.

	//invert clock input, only in bypass mode. when fs_div = 0 is in bypass mode.
	short invert;
	/*sets the number of input clock periods for which the
	frame sync output is high. Pulse width should be less than the divisor of the frame
	sync*/
	short   width;


	short sclk_div;
	//0 or 1: PCG is in bypass mode
	short fs_div;
};


struct SRCDef{
	short enable;
	short format ; //0-left-justified ,1-iis,2-tdm,3-right justified.
	short wordLen; //0-24bit,1-16bit.
	short ratio; //output / input ,Q11.
};

struct RouteDef{
	unsigned short source;
	unsigned short dest;
};

struct DSPConfig{
	unsigned short mDualDsp;
	unsigned short mDspIndex;
	unsigned short mLevelReportInt;  //µçƽÉϱ¨Ê±¼ä
	unsigned short mIntrNo;  ////master interrupt no
	unsigned short mDanteRxNum;  //unused
	unsigned short mDanteTxNum;  //unused

	unsigned short mConvertUnit; //ת»»µ¥Î», DSPĬÈÏÊÇÌî0-dBFS£¬×ª»»µ½ÆäËûµ¥Î»£¬Ðè¼ÓÉÏ»ò¼õÈ¥¶àÉÙ
	unsigned short pad[5];

	unsigned short mRouteNum;
	unsigned short mSampleNum;

	unsigned int mSampleRate;

	//sport0a,0b,1a,1b...7a,7b,¹²16¸ö, Ç°8¸öÓÃÓÚdai0£¬ºó8¸öÓÃÓÚdai1.
	struct SportDef sports[16];
	//Ç°2¸öpcgÓÃÓÚdai0£¬ ºó2¸öÓÃÓÚdai1.
	struct PCGDef   pcgs[4];
	struct RouteDef routes[96]; //variable
	//Ç°4¸ösrcÓÃÓÚdai0,ºó4¸ösrcÓÃÓÚdai1
	struct SRCDef   srcs[8];  //src0.
	struct LinkPortDef linkport[2];
};

void spu_config(void);
void pinmux_config(void);
int  DDR_config(void);
void DAI_config(void);

void lp_pinmux_config(void);

void RouteConfig(struct RouteDef* items, u32 nItems);
void SportsConfig(struct SportDef sports[8]);
void PCGsConfig(struct PCGDef pcgs[4]);
void SRCsConfig(int group , struct SRCDef src[8]);
void LinportConfig(struct LinkPortDef lp[2]);

#ifdef __cplusplus
}
#endif
//#endif /* DRV_BOARD_H_ */