#include <def21489.h>

.global _InitPLL;
.global _InitSDRAM;
.global _InitAMI;

.section/pm seg_pmco;

_InitPLL:
// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
// Fcclk = (CLKIN * 2 * M) / (N * D)
// VCO max frequency = 800 GHz
// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1


// Core clock = (25MHz * 2* 16) /(2 * 1) = 400 MHz
// SDRAM clock = 400 / 2.5 = 160 MHz.

	ustat3 = PLLM16|PLLD2|SDCKR2_5;
changePLL:

    bit set ustat3 DIVEN;
    dm(PMCTL) = ustat3;
    
    bit set ustat3 PLLBP; //Place the PLL in bypass mode.
	bit clr ustat3 DIVEN; //Clear the DIVEN bit while placing the PLL in bypass mode.
    dm(PMCTL) = ustat3;

     // Wait for at least 4096 cycles for the pll to lock
    lcntr = 5000, do loopend2 until lce;
loopend2:     nop;

    ustat3 = dm(PMCTL);	//Reading the PMCTL register will return the DIVEN bit value as zero.
    bit clr ustat3 PLLBP; //Take the PLL out of bypass mode.
    dm(PMCTL) = ustat3;
    
    lcntr = 16, do loopend3 until lce;
loopend3:     nop;

_InitPLL.end: rts;		

_InitSDRAM:
// SDRAM memory on EZ-KIT - MT48LC16M16A2-6A
//5.4ns @ CL = 3 ,167 MHz speed
// Parameters 
// Config - 64M x 16(16M x 16 x 4)
// Speed -        167 MHz
// CAS Latency -   3
// Row addressing - 8K(A0-A12)
// Column addressing - 512(A0-A8)
// No of Banks - 4

//tRAS - 42ns
//tRCD - 18ns
//tRP - 18ns
//tRC - 60ns( tRP + tRAS >= tRC)
//tWR - (1CLK + 6ns)/12

//For the 160 MHz case, tSDCLK = 1/160 MHz = 6.25ns 
// CAS Latency = 3
// tRCD = 18 / 6.25 = 3(2.88)
// tRP = 18 / 6.25 = 3(2.88)
// tRC = 60 / 6.25 = 10(9.6)
// tRAS = 42/ 6.25 = 7(6.72)
// tWR = (6.25 + 6)/ 12 = 2(1.02)
// fSDCLK = 160 MHz
// tREF=  64ms
// NRA = 8192

// RDIV = ((f SDCLK X t REF)/NRA) - (t RAS + t RP)
// RDIV = (((160 X 10^6 x 64 x 10^-3)/8192) - (7 + 3))
// RDIV = 1240 = 0x4D8

#define RDIV	(0x4D8)

	ustat1 = dm(SYSCTL);
	bit set ustat1 MSEN;
	dm(SYSCTL) = ustat1;

	// Mapping Bank 0 to SDRAM
	ustat1 = dm(EPCTL);
	bit set ustat1 B0SD;
	bit clr ustat1 B1SD|B2SD|B3SD;
	dm(EPCTL) = ustat1;
	
	ustat1 = RDIV; 
	bit set ustat1 SDROPT | BIT_17; // Enabling SDRAM read optimization
									// Setting the Modify to 1
	dm(SDRRC) = ustat1;

	// Programming SDRAM control register	
	ustat1 = 0;
	bit set ustat1 SDCL3|SDTRAS7|SDTRP3|SDCAW9|SDPSS|SDTWR2|SDTRCD3|SDRAW13|X16DE;
	dm(SDCTL) = ustat1;
	
	r0 = dm(0x200000);
	nop;
	nop;
	nop;
	nop;
	
_InitSDRAM.end: rts;

_InitAMI:
	ustat1 = dm(SYSCTL);
	bit set ustat1 EPDATA32;
	dm(SYSCTL) = ustat1;
	
	// Flash is connected on Bank 1 
	// Programming maximum waitstates
	ustat1 = AMIEN | BW8 | WS31 ;
	dm(AMICTL1) = ustat1;
	
	// SRAM is connected on Bank 2
	// SRAM part used - IS61WV102416BLL
	// As per datasheet access time is 10 ns, 8ns
	// Programming waitstates = 2
	ustat1 = AMIEN | BW16 | WS2 ;
	dm(AMICTL3) = ustat1;
	
_InitAMI.end: rts;