#include <def21489.h>


.section/pm     seg_pmco;    // the kernel must reside in a single input_section
.global _initPLL_SDRAM2;

//==============================  USER_INIT  ===================================
// This space is provided for the user to insert code. This is only required
// when a system requires a custom configuration for the DSP.  

// These External Port and PLL settings are for the ADSP-21469 EZkit.
// Update the settings below to match the requirements for the target board.
//------------------------------------------------------------------------------
_initPLL_SDRAM2:




	// Set INDIV bit in PMCTL register
	USTAT1 = dm(PMCTL);
	bit set USTAT1  INDIV;  
	dm(PMCTL) = USTAT1;

	// Program PLL multiplier to same value as CLK_CFGx pins/previously programmed value in software……
	dm(PMCTL) = USTAT1;

	// Place PLL in bypass mode
	bit set USTAT1  PLLBP;  
	dm(PMCTL) = USTAT1;

	// Wait recommended number of cycles
	lcntr=4096, do loopwait1 until lce;
loopwait1:
	nop;

	// Bring PLL out of bypass mode by clearing PLLBP bit
	bit clr USTAT1 PLLBP; 
	dm(PMCTL) = USTAT1; 

	// Wait for PLL bypass exit
	lcntr=16, do loopwait2 until lce;
loopwait2:
	nop;

	USTAT1 = dm(PMCTL);
	// Clear the previous PLL multiplier
	bit clr USTAT1 PLLM63;
	// Clear the INDIV bit
	bit clr USTAT1 INDIV;
	// or set the INDIV bit
	// bit set USTAT1 INDIV;
	dm(PMCTL) = USTAT1;
	
	// Set PMCTL with the desired values

// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
// Fcclk = (CLKIN * 2 * M) / (N * D)
// VCO frequency = 2*fINPUT*PLLM = 2*25*16 = 800 <= fVCOmax (800 MHz)
// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1


// Core clock = (25 MHz * 2* 16) /(2 * 1) = 400 MHz
// SDRAM clock = 400 / 2.5 = 160 MHz.

    ustat3 = PLLM16|PLLD2|SDCKR2_5|DIVEN;
    dm(PMCTL) = ustat3;

    bit set ustat3 PLLBP;	//Setting the PLLBP bit
    bit clr ustat3 DIVEN;	//Clearing the DIVEN bit
    dm(PMCTL) = ustat3;		//Putting the PLL into bypass mode

     // Wait for at least 4096 cycles for the pll to lock
    lcntr = 5000, do loopend2 until lce;
loopend2:     nop;

    ustat3 = dm(PMCTL);	
    bit clr ustat3 PLLBP; 	//Bringing the PLL out of bypass mode
    dm(PMCTL) = ustat3;
	
   lcntr=16, do again until lce; //Wait for around 15 CCLK cycles for output dividers to stabilize
again:  nop;

    ustat1 = dm(PMCTL1);
bit set ustat1 FFTACCSEL;
dm(PMCTL1) = ustat1;
nop;
nop;
nop;
nop;	

_initPLL_SDRAM2.end:


//==============================================================================/