#include "global.h"
#include <sru.h>

asm("#include <def21489.h>");
	
void clearDAIpins(void)
{
//------------------------------------------------------------------------
//  Tie the pin buffer inputs LOW for all DAI pins.  Even though
//    these pins are inputs to the SHARC, tying unused pin buffer inputs
//    LOW is "good coding style" to eliminate the possibility of
//    termination artifacts internal to the IC.  Note that signal
//    integrity is degraded only with a few specific SRU combinations.
//    In practice, this occurs VERY rarely, and these connections are
//    typically unnecessary.  This is GROUP D
    SRU(LOW, DAI_PB01_I);
    SRU(LOW, DAI_PB02_I);
    SRU(LOW, DAI_PB03_I);
    SRU(LOW, DAI_PB04_I);
    SRU(LOW, DAI_PB05_I);
    SRU(LOW, DAI_PB06_I);
    SRU(LOW, DAI_PB07_I);
    SRU(LOW, DAI_PB08_I);
    SRU(LOW, DAI_PB09_I);
    SRU(LOW, DAI_PB10_I);
    SRU(LOW, DAI_PB11_I);
    SRU(LOW, DAI_PB12_I);
    SRU(LOW, DAI_PB13_I);
    SRU(LOW, DAI_PB14_I);
    SRU(LOW, DAI_PB15_I);
    SRU(LOW, DAI_PB16_I);
    SRU(LOW, DAI_PB17_I);
    SRU(LOW, DAI_PB18_I);
    SRU(LOW, DAI_PB19_I);
    SRU(LOW, DAI_PB20_I);

//------------------------------------------------------------------------
//  Tie the pin buffer enable inputs LOW for all DAI pins so
//  that they are always input pins.  This is GROUP F.
    SRU(LOW, PBEN01_I);
    SRU(LOW, PBEN02_I);
    SRU(LOW, PBEN03_I);
    SRU(LOW, PBEN04_I);
    SRU(LOW, PBEN05_I);
    SRU(LOW, PBEN06_I);
    SRU(LOW, PBEN07_I);
    SRU(LOW, PBEN08_I);
    SRU(LOW, PBEN09_I);
    SRU(LOW, PBEN10_I);
    SRU(LOW, PBEN11_I);
    SRU(LOW, PBEN12_I);
    SRU(LOW, PBEN13_I);
    SRU(LOW, PBEN14_I);
    SRU(LOW, PBEN15_I);
    SRU(LOW, PBEN16_I);
    SRU(LOW, PBEN17_I);
    SRU(LOW, PBEN18_I);
    SRU(LOW, PBEN19_I);
    SRU(LOW, PBEN20_I);
}





void InitDAI()
{
    clearDAIpins();
    
    
  	SRU(DAI_PB16_O, SPORT0_CLK_I); //tdm
  	SRU(DAI_PB16_O, SPORT1_CLK_I); //tdm
  	
    SRU(DAI_PB14_O, SPORT0_FS_I); //tdm
	SRU(DAI_PB14_O, SPORT1_FS_I); //tdm
	
    //input iis
 	SRU(DAI_PB07_O, SPORT1_DA_I); //0-1  
    SRU(DAI_PB13_O, SPORT1_DB_I); //2-3

    //output
    SRU(HIGH, PBEN10_I);
    SRU(SPORT0_DA_O, DAI_PB10_I);    
    SRU(HIGH, PBEN20_I);
    SRU(SPORT0_DB_O, DAI_PB20_I);   
   
           
	//usb audio
#if 0
	SRU(DAI_PB05_O, SPORT5_FS_I);
	SRU(DAI_PB06_O, SPORT5_CLK_I);
	SRU(DAI_PB05_O, SPORT4_FS_I);
	SRU(DAI_PB06_O, SPORT4_CLK_I);
	
	SRU(DAI_PB09_O, SPORT5_DA_I); //usb in
	SRU(HIGH, PBEN17_I);
	SRU(SPORT4_DA_O, DAI_PB17_I); //usb out
#else/////////////////////////////////////	
	SRU(DAI_PB06_O,SRC0_CLK_IP_I);
	SRU(DAI_PB05_O,SRC0_FS_IP_I);	
 	SRU(DAI_PB09_O,SRC0_DAT_IP_I);

	SRU(DAI_PB15_O,SRC0_CLK_OP_I);
	SRU(DAI_PB15_O,SPORT5_CLK_I);
	SRU(DAI_PB12_O,SRC0_FS_OP_I);
	SRU(DAI_PB12_O,SPORT5_FS_I);

	SRU(SRC0_DAT_OP_O,SPORT5_DA_I);

	//usb output.
	SRU(DAI_PB15_O,SPORT4_CLK_I);
	SRU(DAI_PB12_O,SPORT4_FS_I);
	SRU(DAI_PB15_O,SRC1_CLK_IP_I);
	SRU(DAI_PB12_O,SRC1_FS_IP_I);
 	SRU(SPORT4_DA_O,SRC1_DAT_IP_I);
	
 	SRU(DAI_PB06_O,SRC1_CLK_OP_I);
	SRU(DAI_PB05_O,SRC1_FS_OP_I);

	SRU(HIGH, PBEN17_I);
	SRU(SRC1_DAT_OP_O,DAI_PB17_I);
#endif
	 
	//pcg
	 SRU(DAI_PB03_O,PCG_EXTA_I);
	 SRU(PCG_CLKA_O,PCG_EXTB_I);
	// SRU(DAI_PB03_O,PCG_EXTC_I); //iis
	 
	 SRU(HIGH, PBEN16_I); //clk
	 SRU(PCG_FSB_O,DAI_PB16_I);
	 SRU(HIGH, PBEN14_I); //fs
	 SRU(PCG_FSA_O,DAI_PB14_I);
	 
	 SRU(HIGH, PBEN15_I); //iis clk
	 SRU(PCG_CLKC_O,DAI_PB15_I);
	 SRU(HIGH, PBEN12_I); //iis fs
	 SRU(PCG_FSC_O,DAI_PB12_I);
	 SRU(DAI_PB03_O,PCG_EXTC_I);
}


void InitSRC(void)
{

  //============================================================
    //
    // Configure SRC Control Register (SRCCTL0).
    //
    //    SRC1_IN_I2S : SRC1 Serial Input Format= I2S mode
    //    SRC1_OUT_I2S: SRC1 Serial Output Format= I2S mode
    //    SRC1_OUT_24 : Output Word Length= 24 bits  
    //------------------------------------------------------------
	*pSRCCTL0 = SRC0_IN_I2S | SRC0_OUT_I2S | SRC0_OUT_24 | SRC1_IN_I2S | SRC1_OUT_I2S | SRC1_OUT_24;
	//*pSRCCTL0 = SRC0_IN_LJ | SRC0_OUT_LJ | SRC0_OUT_24 |SRC1_IN_LJ | SRC1_OUT_LJ | SRC1_OUT_24;
	// Enable SRC1 in a different cycle than setting the configuration
	*pSRCCTL0 |= SRC0_ENABLE|SRC1_ENABLE;
//*pSRCCTL0 = SRC0_SMODEIN0 | SRC0_SMODEOUT0 | SRC0_ENABLE ;
}