/*
 * board.c
 *
 *  Created on: 2021Äê9ÔÂ1ÈÕ
 *      Author: graydon
 */
#include <stdio.h>
#include <signal.h>
#include <SRU.h>
#include <def1802.h>
#include <cdef1802.h>
//#include <def21489.h>
//#include <cdef21489.h>
#include "board.h"
#include "config.h"
#include "sport.h"
#include "string.h"

//static ubool has_dante = ufalse;

void pinmux_config(void)
{
	int i ,j ;
	//GPIO
	SRU(HIGH, DPI_PBEN11_I); //0-busy,1-idle
	SRU(HIGH, DPI_PBEN12_I); //0-send, 1-recv
	SRU(LOW,DPI_PB12_I);
	SRU(LOW,DPI_PB11_I);

	SRU(HIGH,DPI_PBEN13_I);//led
	SRU(HIGH,DPI_PBEN14_I);
	for(i=0;i<3;i++) {
		SRU(LOW,DPI_PB13_I);
		SRU(LOW,DPI_PB14_I);
		for(j=0 ;j < 2000000 ;j++);
		SRU(HIGH,DPI_PB13_I);
		SRU(HIGH,DPI_PB14_I);
		for(j=0 ;j < 2000000 ;j++);
	}

}

void InitPCG(void);
void InitSRC(void);
void SportsConfig(void);

void Audio_Config(void)
{
	SRU(DAI_PB02_O, SPORT0_CLK_I);
	SRU(DAI_PB02_O, SPORT1_CLK_I);
	SRU(DAI_PB02_O, SPORT2_CLK_I);
	SRU(DAI_PB02_O, SPORT3_CLK_I);
//	SRU(DAI_PB02_O, SPORT4_CLK_I);
//	SRU(DAI_PB02_O, SPORT5_CLK_I);
//	SRU(DAI_PB02_O, SPORT6_CLK_I);
//	SRU(DAI_PB02_O, SPORT7_CLK_I);

	SRU(DAI_PB01_O, SPORT0_FS_I);
	SRU(DAI_PB01_O, SPORT1_FS_I);
	SRU(DAI_PB01_O, SPORT2_FS_I);
	SRU(DAI_PB01_O, SPORT3_FS_I);
//	SRU(DAI_PB01_O, SPORT4_FS_I);
//	SRU(DAI_PB01_O, SPORT5_FS_I);
//	SRU(DAI_PB01_O, SPORT6_FS_I);
//	SRU(DAI_PB01_O, SPORT7_FS_I);

	//analog input
	SRU(DAI_PB17_O, SPORT1_DA_I);
	SRU(DAI_PB14_O, SPORT1_DB_I);
	SRU(DAI_PB08_O, SPORT3_DA_I);
	SRU(DAI_PB10_O, SPORT3_DB_I);

	//analog output
	SRU(HIGH, PBEN18_I);  //OUT0
	SRU(SPORT0_DA_O, DAI_PB18_I);
	SRU(HIGH, PBEN04_I);  //OUT1
	SRU(SPORT0_DB_O, DAI_PB04_I);
	SRU(HIGH, PBEN20_I);  //OUT2
	SRU(SPORT2_DA_O, DAI_PB20_I);
	SRU(HIGH, PBEN09_I);  //OUT3
	SRU(SPORT2_DB_O, DAI_PB09_I);

#if 1
	// SRC ÍâΧʱÖÓ
	SRU(DAI_PB03_O, SRC0_CLK_IP_I);
	SRU(DAI_PB13_O, SRC0_FS_IP_I);
	SRU(DAI_PB03_O, SRC1_CLK_OP_I);
	SRU(DAI_PB13_O, SRC1_FS_OP_I);


	// SRC ÄÚ²¿Ê±ÖÓ
	SRU(DAI_PB02_O, SPORT4_CLK_I);
	SRU(DAI_PB02_O, SPORT5_CLK_I);
	SRU(DAI_PB01_O, SPORT4_FS_I);
	SRU(DAI_PB01_O, SPORT5_FS_I);

	SRU(DAI_PB02_O, SRC0_CLK_OP_I);
	SRU(DAI_PB01_O, SRC0_FS_OP_I);
	SRU(DAI_PB02_O, SRC1_CLK_IP_I);
	SRU(DAI_PB01_O, SRC1_FS_IP_I);


	// DATAÊäÈëASRC
	SRU(DAI_PB07_O, SRC0_DAT_IP_I);
	SRU(SRC0_DAT_OP_O, SPORT5_DA_I);

	// ASRCÊä³öDATA
	SRU(SPORT4_DA_O, SRC1_DAT_IP_I);

	SRU(HIGH, PBEN19_I);
	SRU(SRC1_DAT_OP_O, DAI_PB19_I);
#else
	SRU(DAI_PB03_O, SPORT4_CLK_I);
	SRU(DAI_PB03_O, SPORT5_CLK_I);
	SRU(DAI_PB13_O, SPORT5_FS_I);
	SRU(DAI_PB13_O, SPORT5_FS_I);

	SRU(DAI_PB19_O, SPORT5_DA_I);

	SRU(HIGH, PBEN07_I);
	SRU(SPORT4_DA_O, DAI_PB07_I);
#endif

	//CLOCK
	SRU(HIGH, PBEN02_I); //clk
	SRU(HIGH, PBEN01_I); //fs
	SRU(PCG_CLKC_O,DAI_PB02_I);
	SRU(PCG_FSC_O,DAI_PB01_I);

	SRU(DAI_PB06_O,PCG_EXTC_I);

	InitPCG();
	InitSRC();
	SportsConfig();
}


void SportsConfig(void)
{
#if 1
	int i ;
	struct SportDef sports[8];

	memset(sports , 0, sizeof(struct SportDef)*8);

	for (i = 0 ;i < 6;i ++){
		sports[i].clke = 0;
		sports[i].enable = 1;
		sports[i].enable_sec = 1;
		sports[i].lfs = 0;
		sports[i].mfd = 0;
		sports[i].opmode = 1;
		sports[i].slots = 2;
		sports[i].spid = i;
		sports[i].vld_a = 2;
		sports[i].vld_b = 2;
		sports[i].rx = i&0x1;
		sports[i].interrupt =0 ;
	}

	sports[5].interrupt = 1; //sport 1 interrupt.

	sports[4].enable_sec = 0;
	sports[4].clke = 0;
	sports[4].lfs = 0;
	sports[5].enable_sec = 0;
	sports[5].clke = 0;
	sports[5].lfs = 0;

	for(i = 0; i < 8 ; i++) {
		if(sports[i].enable && sports[i].spid < 8) {
			sport_config(&sports[i]);
		}
	}
#else
	InitSPORT(0,0);
#endif
}


void InitPCG(void)
{
	int n,r0 ;
	int fs_div = MCLK/SAMPLE_RATE;
	int sclk_div = MCLK/(SAMPLE_RATE*32*8);
	int sclk_div_48k = MCLK/(SAMPLE_RATE*32*2);

  	//TDM
	*pPCG_CTLA1 =0 ; *pPCG_CTLA0 =0;
		 for (n=0; n<16; n++)asm("NOP;");


	r0 = sclk_div | CLKASOURCE | FSASOURCE;
	*pPCG_CTLA1 = r0 ;

	r0 =  fs_div | ENFSA | ENCLKA;
	*pPCG_CTLA0 = r0;


	//bypass mode PCGB , get invert sclk
	*pPCG_CTLB1 =0 ; *pPCG_CTLB0 =0;
		 for (n=0; n<16; n++)asm("NOP;");

	*pPCG_PW1 = 2| INVFSB ;

	r0 = sclk_div | CLKBSOURCE | FSBSOURCE;
	*pPCG_CTLB1 = r0;

	r0 =  ENFSB | ENCLKB;
	*pPCG_CTLB0 = r0;

	//IIS
	*pPCG_CTLC1 =0 ; *pPCG_CTLC0 =0;
	     for (n=0; n<16; n++)asm("NOP;");

  	r0 =  sclk_div_48k| CLKCSOURCE | FSCSOURCE | ((sclk_div_48k/2)<<20);
  	*pPCG_CTLC1 = r0 ;

  	r0 =  fs_div | ENFSC | ENCLKC;
  	*pPCG_CTLC0 = r0;
}

void InitSRC(void)
{

  //============================================================
    //
    // Configure SRC Control Register (SRCCTL0).
    //
    //    SRC1_IN_I2S : SRC1 Serial Input Format= I2S mode
    //    SRC1_OUT_I2S: SRC1 Serial Output Format= I2S mode
    //    SRC1_OUT_24 : Output Word Length= 24 bits
    //------------------------------------------------------------
	*pSRCCTL0 = SRC0_IN_I2S | SRC0_OUT_I2S | SRC0_OUT_24 | SRC1_IN_I2S | SRC1_OUT_I2S | SRC1_OUT_24;
	// Enable SRC1 in a different cycle than setting the configuration
	*pSRCCTL0 |= SRC0_ENABLE|SRC1_ENABLE;


//	*pSRCCTL1 = SRC2_IN_I2S | SRC2_OUT_I2S | SRC2_OUT_24 | SRC3_IN_I2S | SRC3_OUT_I2S | SRC3_OUT_24;
//	// Enable SRC1 in a different cycle than setting the configuration
//	*pSRCCTL1 |= SRC2_ENABLE|SRC3_ENABLE;
}

//void PCGsConfig(struct PCGDef pcgs[4])
//{
//#if 0
//	u32 i;
//
//	volatile u32* pcg_pw[4] = {pPCG_PW1, pPCG_PW1 ,pPCG_PW2 ,pPCG_PW2};
//	volatile u32* pcg_ctlc0[4] = {pPCG_CTLA0, pPCG_CTLB0 ,pPCG_CTLC0 ,pPCG_CTLD0};
//	volatile u32* pcg_ctlc1[4] = {pPCG_CTLA1, pPCG_CTLB1 ,pPCG_CTLC1 ,pPCG_CTLD1};
//
//	*pPCG_PW1 = 0; *pPCG_PW2 = 0;
//
//	for(i = 0; i < 4; i++) {
//		if (pcgs[i].enable ) {
//			s32 n,r0 ;
//
//			*pcg_ctlc1[i] =0 ; *pcg_ctlc0[i] =0;
//			 for (n=0; n<16; n++)asm("NOP;");
//
//			 if(pcgs[i].opmode) {
//				 if(pcgs[i].fs_div > 0) {
//					 *pcg_pw[i] |= (i&0x1)?(pcgs[i].width<<16):pcgs[i].width;
//				 }
//				 else if(pcgs[i].invert){
//					 //bypass mode.
//					 *pcg_pw[i] |= (i&0x1)?(1<<17):(1<<1);
//				 }
//
//				 r0 =  pcgs[i].sclk_div| (1<<30) | (1<<31) ;
//			 }
//			 else {
//				 r0 =  pcgs[i].sclk_div| (1<<30) | (1<<31) | ((pcgs[i].sclk_div/2)<<20);
//			 }
//			*pcg_ctlc1[i] = r0 ;
//
//			r0 =  pcgs[i].fs_div | (1<<30) | (1<<31) ;
//			*pcg_ctlc0[i] = r0;
//		}
//	}
//#else
//	InitPCG();
//#endif
//}


//void SRCsConfig(struct SRCDef src[4])
//{
//	u32 reg[4] = {0 ,0, 0, 0};
//
//	for(u32 i = 0 ;i < 4  ;i ++) {
//		if(src[i].enable) {
//			switch (src[i].format) {
//			case 0:
//				break;
//			case 1:
//				//iis
//				reg[i] = (1<<2) | (1<<10) | (1<<15);
//				break;
//			case 2:
//				//tdm
//				reg[i] = (2<<2) | (2<<10) | (1<<15);
//				break;
//			case 3:
//				break;
//			}
//		}
//	}
//	*pSRCCTL0 = reg[0]|(reg[1]<<16);
//	*pSRCCTL1 = reg[2]|(reg[3]<<16);
//
//}



void DAI_config()
{
	SRU(LOW, DAI_PB01_I);
	SRU(LOW, DAI_PB02_I);
	SRU(LOW, DAI_PB03_I);
	SRU(LOW, DAI_PB04_I);
	SRU(LOW, DAI_PB05_I);
	SRU(LOW, DAI_PB06_I);
	SRU(LOW, DAI_PB07_I);
	SRU(LOW, DAI_PB08_I);
	SRU(LOW, DAI_PB09_I);
	SRU(LOW, DAI_PB10_I);
	SRU(LOW, DAI_PB11_I);
	SRU(LOW, DAI_PB12_I);
	SRU(LOW, DAI_PB13_I);
	SRU(LOW, DAI_PB14_I);
	SRU(LOW, DAI_PB15_I);
	SRU(LOW, DAI_PB16_I);
	SRU(LOW, DAI_PB17_I);
	SRU(LOW, DAI_PB18_I);
	SRU(LOW, DAI_PB19_I);
	SRU(LOW, DAI_PB20_I);

//------------------------------------------------------------------------
//  Tie the pin buffer enable inputs LOW for all DAI pins so
//  that they are always input pins.  This is GROUP F.
	SRU(LOW, PBEN01_I);
	SRU(LOW, PBEN02_I);
	SRU(LOW, PBEN03_I);
	SRU(LOW, PBEN04_I);
	SRU(LOW, PBEN05_I);
	SRU(LOW, PBEN06_I);
	SRU(LOW, PBEN07_I);
	SRU(LOW, PBEN08_I);
	SRU(LOW, PBEN09_I);
	SRU(LOW, PBEN10_I);
	SRU(LOW, PBEN11_I);
	SRU(LOW, PBEN12_I);
	SRU(LOW, PBEN13_I);
	SRU(LOW, PBEN14_I);
	SRU(LOW, PBEN15_I);
	SRU(LOW, PBEN16_I);
	SRU(LOW, PBEN17_I);
	SRU(LOW, PBEN18_I);
	SRU(LOW, PBEN19_I);
	SRU(LOW, PBEN20_I);



}