From 8758151dcdb0f89e362dd297405a384d3a034380 Mon Sep 17 00:00:00 2001
From: chenlh <2008get@163.com>
Date: 星期三, 28 一月 2026 20:21:37 +0800
Subject: [PATCH] 天宫输入源模块设置时爆音及参数拷贝更新
---
src/tg/tg_adapter.cpp | 123 ++++++++++++++++++++++++++--------------
1 files changed, 79 insertions(+), 44 deletions(-)
diff --git a/src/tg/tg_adapter.cpp b/src/tg/tg_adapter.cpp
index 6b51fdb..6738e72 100644
--- a/src/tg/tg_adapter.cpp
+++ b/src/tg/tg_adapter.cpp
@@ -4,35 +4,36 @@
s32 tg_hw_adapter_t::get_physical_channel(s32 input , s32 logic_channel)
{
- //s32 phy_channel[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19};
- if(input) {
- s32 input_num = ana_input_num + dante_input_num ;
- if(logic_channel < ana_input_num) {
- //analog
- return logic_channel + 1;
- }
- else if(logic_channel < input_num) {
- //dante
- return 19 + (logic_channel-ana_input_num);
- }
- else {
- //usb
- return 17 + (logic_channel-input_num);
- }
- }
- else {
- s32 output_num = ana_output_num + dante_output_num ;
- //output
- if(logic_channel < ana_output_num) {
- return logic_channel +1;
- }
- else if(logic_channel < output_num) {
- return 19 + (logic_channel-ana_output_num);
- }
- else {
- return 17 + (logic_channel-output_num);
- }
- }
+ if(input) {
+ s32 input_num = ana_input_num + dante_input_num;
+ if(logic_channel < ana_input_num) {
+ //analog
+ return logic_channel + 1;
+ }
+ else if(logic_channel < input_num) {
+ //dante
+ return 19 + (logic_channel - ana_input_num);
+ }
+ else {
+ //usb
+ return (logic_channel > input_num) ? 17 : 18;
+ }
+ }
+ else { //output
+ s32 output_num = ana_output_num + dante_output_num;
+ if(logic_channel < ana_output_num) {
+ //analog
+ return logic_channel + 1;
+ }
+ else if(logic_channel < output_num) {
+ //dante
+ return 19 + (logic_channel - ana_output_num);
+ }
+ else {
+ //usb
+ return ((logic_channel > output_num) ? 17 : 18);
+ }
+ }
}
//物理buffer定义顺序是16通道模拟+2通道USB+32通道Dante.
@@ -106,8 +107,8 @@
conf->sports[i].clke = utrue;
conf->sports[i].enable = utrue;
conf->sports[i].enable_sec = ufalse;
- conf->sports[i].lfs = ufalse;
- conf->sports[i].mfd = 1;
+ conf->sports[i].lfs = ufalse; // The USB left and right channels can be swapped.
+ conf->sports[i].mfd = 0;
conf->sports[i].opmode = 1 ; //i2s
conf->sports[i].rx = ufalse;
conf->sports[i].slots = 2;
@@ -118,25 +119,59 @@
conf->sports[4].rx = utrue;
//USB pcg.
-// conf->pcgs[1].enable = utrue;
-// conf->pcgs[1].opmode = 0;
-// conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
-// conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
-// AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
+ conf->pcgs[1].enable = utrue;
+ conf->pcgs[1].opmode = 0;
+ conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
+ conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
+ AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
+ // route
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_AFS_I);
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_BFS_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_ACLK_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_BCLK_I);
// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN09_I);//fs
// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN08_I);//sclk
// AddRoute(SourceSignal::PCG_FSB_O, DestSignal::DAI0_PB09_I);
// AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::DAI0_PB08_I);
- AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
- AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
- AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
- AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);
+// AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
+// AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
+// AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
+// AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);
- AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I);
+// AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I); // usb output
+// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
+// AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I); // usb input
+
+ // usb asrc
+ conf->srcs[0].enable = utrue;
+ conf->srcs[0].format = 1;
+ conf->srcs[0].wordLen = 0;
+ conf->srcs[0].ratio = 1; // usb input
+
+ conf->srcs[1].enable = utrue;
+ conf->srcs[1].format = 1;
+ conf->srcs[1].wordLen = 0;
+ conf->srcs[1].ratio = 0; // usb output
+
+ // usb input / asrc input
+ AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC0_FS_IP_I);
+ AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC0_CLK_IP_I);
+ AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SRC0_DAT_IP_I);
+ // usb input / asrc output
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC0_FS_OP_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC0_CLK_OP_I);
+ AddRoute(SourceSignal::SRC0_DAT_OP_O, DestSignal::SPT2_AD0_I);
+ // usb output / asrc input
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC1_FS_IP_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC1_CLK_IP_I);
+ AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::SRC1_DAT_IP_I);
+ // usb output / asrc output
+ AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC1_FS_OP_I);
+ AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC1_CLK_OP_I);
AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
- AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I);
+ AddRoute(SourceSignal::SRC1_DAT_OP_O, DestSignal::DAI0_PB10_I);
//Dante Slave
//MCLK(DAI1_2),LRCLK(DAI1_20),SCLK(DAI1_19)
@@ -152,8 +187,8 @@
conf->sports[i].mfd = 1;
conf->sports[i].opmode = 0 ; //tdm
conf->sports[i].rx = ufalse;
- conf->sports[i].slots = 16;
- conf->sports[i].vld = 16;
+ conf->sports[i].slots = 8;
+ conf->sports[i].vld = 8;
conf->sports[i].follow_intr_no = intr_sport_no(8);
}
conf->sports[8].interrupt = utrue;
--
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