From 8445c54f01777513912d4c6d36c28e92a0ff33a0 Mon Sep 17 00:00:00 2001
From: chenlh <2008get@163.com>
Date: 星期四, 18 九月 2025 14:40:53 +0800
Subject: [PATCH] 首轮测试代码提交
---
src/tg/tg_adapter.cpp | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------
1 files changed, 106 insertions(+), 14 deletions(-)
diff --git a/src/tg/tg_adapter.cpp b/src/tg/tg_adapter.cpp
index 6b51fdb..eb293ab 100644
--- a/src/tg/tg_adapter.cpp
+++ b/src/tg/tg_adapter.cpp
@@ -2,37 +2,77 @@
#include "tg_config.h"
#include "tg_adapter.h"
+//参数logic_channel逻辑通道从0开始.
s32 tg_hw_adapter_t::get_physical_channel(s32 input , s32 logic_channel)
{
+<<<<<<< HEAD
+ if(input) {
+ s32 input_num = ana_input_num + dante_input_num ;
+ if(logic_channel < ana_input_num) {
+ //analog
+ return logic_channel + 1;
+ }
+ else if(logic_channel < input_num) {
+ //dante
+ return 19 + (logic_channel - ana_input_num);
+ }
+ else {
+ //usb
+// return 17 + (logic_channel - input_num);
+ return (logic_channel > input_num) ? 17 : 18;
+ }
+ }
+ else { //output
+ s32 output_num = ana_output_num + dante_output_num ;
+ //analog
+ if(logic_channel < ana_output_num) {
+ return logic_channel + 1;
+ }
+ else if(logic_channel < output_num) {
+ //dante
+ return 19 + (logic_channel - ana_output_num);
+ }
+ else {
+ //usb
+// return 17 + (logic_channel - output_num);
+ return (logic_channel > output_num) ? 17 : 18;
+ }
+ }
+=======
//s32 phy_channel[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19};
if(input) {
s32 input_num = ana_input_num + dante_input_num ;
+// s32 local_ch = ana_input_num + usb_input_num; // C H G 18
if(logic_channel < ana_input_num) {
//analog
- return logic_channel + 1;
+ return logic_channel+1;
}
else if(logic_channel < input_num) {
//dante
- return 19 + (logic_channel-ana_input_num);
+ return 19 + (logic_channel - ana_input_num);
}
else {
//usb
- return 17 + (logic_channel-input_num);
+ return 17 + (logic_channel - input_num);
}
}
- else {
+ else { //output
s32 output_num = ana_output_num + dante_output_num ;
- //output
+// s32 local_ch = ana_output_num + usb_output_num; // C H G 18
+ //analog
if(logic_channel < ana_output_num) {
- return logic_channel +1;
+ return logic_channel;
}
else if(logic_channel < output_num) {
- return 19 + (logic_channel-ana_output_num);
+ //dante
+ return 19 + (logic_channel - ana_output_num);
}
else {
- return 17 + (logic_channel-output_num);
+ //usb
+ return 17 + (logic_channel - output_num);
}
}
+>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
}
//物理buffer定义顺序是16通道模拟+2通道USB+32通道Dante.
@@ -106,8 +146,13 @@
conf->sports[i].clke = utrue;
conf->sports[i].enable = utrue;
conf->sports[i].enable_sec = ufalse;
+<<<<<<< HEAD
+ conf->sports[i].lfs = ufalse; // The USB left and right channels can be swapped.
+ conf->sports[i].mfd = 0;
+=======
conf->sports[i].lfs = ufalse;
conf->sports[i].mfd = 1;
+>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
conf->sports[i].opmode = 1 ; //i2s
conf->sports[i].rx = ufalse;
conf->sports[i].slots = 2;
@@ -118,25 +163,67 @@
conf->sports[4].rx = utrue;
//USB pcg.
+<<<<<<< HEAD
+ conf->pcgs[1].enable = utrue;
+ conf->pcgs[1].opmode = 0;
+ conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
+ conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
+ AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
+ // route
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_AFS_I);
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_BFS_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_ACLK_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_BCLK_I);
+=======
// conf->pcgs[1].enable = utrue;
// conf->pcgs[1].opmode = 0;
// conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
// conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
// AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
+>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN09_I);//fs
// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN08_I);//sclk
// AddRoute(SourceSignal::PCG_FSB_O, DestSignal::DAI0_PB09_I);
// AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::DAI0_PB08_I);
- AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
- AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
- AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
- AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);
+// AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
+// AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
+// AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
+// AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);
- AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I);
+// AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I); // usb output
+// AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
+// AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I); // usb input
+
+ // usb asrc
+ conf->srcs[0].enable = utrue;
+ conf->srcs[0].format = 1;
+ conf->srcs[0].wordLen = 0;
+ conf->srcs[0].ratio = 1; // usb input
+
+ conf->srcs[1].enable = utrue;
+ conf->srcs[1].format = 1;
+ conf->srcs[1].wordLen = 0;
+ conf->srcs[1].ratio = 0; // usb output
+
+ // usb input / asrc input
+ AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC0_FS_IP_I);
+ AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC0_CLK_IP_I);
+ AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SRC0_DAT_IP_I);
+ // usb input / asrc output
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC0_FS_OP_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC0_CLK_OP_I);
+ AddRoute(SourceSignal::SRC0_DAT_OP_O, DestSignal::SPT2_AD0_I);
+ // usb output / asrc input
+ AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC1_FS_IP_I);
+ AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC1_CLK_IP_I);
+ AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::SRC1_DAT_IP_I);
+ // usb output / asrc output
+ AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC1_FS_OP_I);
+ AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC1_CLK_OP_I);
AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
- AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I);
+ AddRoute(SourceSignal::SRC1_DAT_OP_O, DestSignal::DAI0_PB10_I);
//Dante Slave
//MCLK(DAI1_2),LRCLK(DAI1_20),SCLK(DAI1_19)
@@ -152,8 +239,13 @@
conf->sports[i].mfd = 1;
conf->sports[i].opmode = 0 ; //tdm
conf->sports[i].rx = ufalse;
+<<<<<<< HEAD
+ conf->sports[i].slots = 8;
+ conf->sports[i].vld = 8;
+=======
conf->sports[i].slots = 16;
conf->sports[i].vld = 16;
+>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
conf->sports[i].follow_intr_no = intr_sport_no(8);
}
conf->sports[8].interrupt = utrue;
--
Gitblit v1.9.3