| | |
| | | #define MSIZE 0 |
| | | #define PSIZE 0 |
| | | |
| | | volatile unsigned char SPI_Tx_BUFFER[SPI_BUFFER_SIZE]; |
| | | volatile unsigned char SPI_Rx_BUFFER[SPI_BUFFER_SIZE]; |
| | | ADI_CACHE_ALIGN volatile unsigned char SPI_Tx_BUFFER[SPI_BUFFER_SIZE]; |
| | | ADI_CACHE_ALIGN volatile unsigned char SPI_Rx_BUFFER[SPI_BUFFER_SIZE]; |
| | | // |
| | | volatile short SPIRxDone =1; |
| | | volatile short SPITxDone =1; |
| | | volatile unsigned short SPIRxCnt =0, SPITxCnt=0; |
| | | |
| | | static void SPIDMA_Handler(uint32_t iid, void* arg) |
| | | { |
| | | if(iid == INTR_SPI2_RXDMA){ |
| | | *pREG_DMA27_STAT |= ENUM_DMA_STAT_IRQDONE ; |
| | | *pREG_DMA26_STAT |= ENUM_DMA_STAT_IRQDONE ; |
| | | |
| | | GPIO_SetOutPut(GPIOA, GPIO_Pin12|GPIO_Pin13, GPIO_HIGH); |
| | | GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_HIGH); |
| | | |
| | | GPIO_SetOutPut(GPIOC, GPIO_Pin4|GPIO_Pin7, GPIO_HIGH); |
| | | |
| | | SPIRxCnt ++ ; |
| | | SPIRxDone = 1; |
| | | SPITxDone = 1; |
| | | } |
| | | // else if(iid == INTR_SPI2_TXDMA) { |
| | | // *pREG_DMA26_STAT |= ENUM_DMA_STAT_IRQDONE ; |
| | | // GPIO_SetOutPut(GPIOC, GPIO_Pin4, GPIO_HIGH); |
| | | // GPIO_SetOutPut(GPIOA, GPIO_Pin12|GPIO_Pin13, GPIO_HIGH); |
| | | // GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_HIGH); |
| | | // |
| | | // GPIO_SetOutPut(GPIOC, GPIO_Pin4|GPIO_Pin7, GPIO_HIGH); |
| | | // |
| | | // SPITxCnt++; |
| | | // SPITxDone = 1; |
| | | // } |
| | | // adi_int_ClearPending(iid); |
| | | adi_int_ClearPending(iid); |
| | | } |
| | | |
| | | |
| | | static void DMAConfig(SPIStatus status) |
| | | { |
| | | adi_osal_EnterCriticalRegion(); |
| | | if(status == SPI_TX) { |
| | | *pREG_DMA26_CFG = (MSIZE<<8) | (PSIZE<<4) | 4 ; |
| | | *pREG_DMA26_CFG = (MSIZE<<8) | (PSIZE<<4) | 4 ; |
| | | *pREG_DMA26_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA26_XMOD = 1; |
| | | *pREG_DMA26_ADDRSTART= (uint32_t)SPI_Tx_BUFFER|MP_OFFSET; |
| | |
| | | *pREG_SPI2_RXCTL |= (1<<0); |
| | | |
| | | } |
| | | |
| | | if(status == SPI_TRX) { |
| | | *pREG_SPI2_CTL =0 ; |
| | | *pREG_SPI2_STAT = 0xffffffff; |
| | | *pREG_DMA26_STAT = 0xffffffff; |
| | | *pREG_DMA27_STAT = 0xffffffff; |
| | | |
| | | *pREG_DMA26_CFG = (MSIZE<<8) | (PSIZE<<4) | 4 ; |
| | | *pREG_DMA26_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA26_XMOD = 1; |
| | | *pREG_DMA26_ADDRSTART= (uint32_t)SPI_Tx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA26_CFG |= 1 ; |
| | | |
| | | *pREG_DMA27_CFG = (1<<1)| (MSIZE<<8) | (PSIZE<<4) | (1<<20) | 4 ; |
| | | *pREG_DMA27_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA27_XMOD = 1; |
| | | *pREG_DMA27_ADDRSTART= (uint32_t)SPI_Rx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA27_CFG |= 1 ; |
| | | |
| | | *pREG_SPI2_CTL= (MASTER<<1)|(0<<3)|(CPHA<<4)|(CPOL<<5)|(1<<6)|(1<<8)|(BITS<<9)|(1<<0); |
| | | *pREG_SPI2_TXCTL = (5<<4) | (1<<0); |
| | | *pREG_SPI2_RXCTL = (1<<4) | (1<<0); |
| | | } |
| | | adi_osal_ExitCriticalRegion(); |
| | | } |
| | | |
| | | void SPI_xfer(int8_t* rx, int8_t* tx, uint32_t len) |
| | |
| | | *pREG_SPI2_CTL = (MASTER<<1)|(0<<3)|(CPHA<<4)|(CPOL<<5)|(1<<6)|(1<<8)|(BITS<<9); |
| | | |
| | | |
| | | *pREG_SPI2_TXCTL = (1<<4); |
| | | *pREG_SPI2_TXCTL = (5<<4); |
| | | *pREG_SPI2_RXCTL = (1<<4); |
| | | |
| | | |
| | |
| | | |
| | | //SPI2_SetTransMode(status); |
| | | adi_sec_SetPriority(INTR_SPI2_RXDMA, 44); |
| | | //interruptcb(INTR_SPI2_RXDMA, SPIDMA_Handler); |
| | | //adi_int_InstallHandler(INTR_SPI2_TXDMA, SPIDMA_Handler, 0, true); |
| | | adi_int_InstallHandler(INTR_SPI2_RXDMA, SPIDMA_Handler, 0, true); |
| | | |
| | | *pREG_SPI2_CTL |= (1<<0); |
| | | //*pREG_SPI2_CTL |= (1<<0); |
| | | //*pREG_SPI2_TXCTL |= (1<<0); |
| | | //*pREG_SPI2_RXCTL |= (1<<0); |
| | | |
| | |
| | | GPIO_SetOutPut(GPIOC, GPIO_Pin7, GPIO_LOW); |
| | | break; |
| | | case SPI_TRX: |
| | | DMAConfig(SPI_TX);SPITxDone = 0 ; |
| | | DMAConfig(SPI_RX);SPIRxDone = 0 ; |
| | | //DMAConfig(SPI_RX);SPIRxDone = 0 ; |
| | | DMAConfig(SPI_TRX);SPITxDone = SPIRxDone = 0 ; |
| | | GPIO_SetOutPut(GPIOA, GPIO_Pin12|GPIO_Pin13, GPIO_LOW); |
| | | GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_LOW); |
| | | GPIO_SetOutPut(GPIOC, GPIO_Pin4|GPIO_Pin7, GPIO_LOW); |