首轮测试版代码常规上传

chenlh

2025-09-18 ab07ada908b82340e7acd899e85a9802cf8a9057

 src/tg/tg_adapter.cpp

@@ -4,27 +4,38 @@

s32 tg_hw_adapter_t::get_physical_channel(s32 input , s32 logic_channel)
{
   //s32 phy_channel[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19};
   if(input) {
      s32 input_num = ana_input_num + dante_input_num ;
      if(logic_channel < ana_input_num) {
         //analog
         return logic_channel;
      }
      else if(logic_channel < input_num) {
         //dante
         return 16+ (logic_channel-ana_input_num);
      }
      else {
         //usb
         return 48 + (logic_channel-input_num);
      }
   }
   else {
      //output
   }

   return 0;
    if(input) {
        s32 input_num = ana_input_num + dante_input_num ;
        if(logic_channel < ana_input_num) {
            //analog
            return logic_channel + 1;
        }
        else if(logic_channel < input_num) {
            //dante
            return 19 + (logic_channel - ana_input_num);
        }
        else {
            //usb
//            return 17 + (logic_channel - input_num);
           return (logic_channel > input_num) ? 17 : 18;
        }
    }
    else {    //output
        s32 output_num = ana_output_num + dante_output_num ;
        //analog
        if(logic_channel < ana_output_num) {
            return logic_channel + 1;
        }
        else if(logic_channel < output_num) {
            //dante
            return 19 + (logic_channel - ana_output_num);
        }
        else {
            //usb
//            return 17 + (logic_channel - output_num);
           return (logic_channel > output_num) ? 17 : 18;
        }
    }
}

//物理buffer定义顺序是16通道模拟+2通道USB+32通道Dante.
@@ -92,17 +103,18 @@
   AddRoute(SourceSignal::SPT0_BD1_O, DestSignal::DAI0_PB12_I);

   //USB Slave. SCLK(DAI0_8),LRCLK(DAI0_9), RX(DAI0_7),TX(DAI0_10)
   for(i =4 ;i < 5; i++) {
   //sport2A<->input;   sport2B<->output
   for(i =4 ;i < 6; i++) {
      conf->sports[i].spid = i;
      conf->sports[i].clke = utrue;
      conf->sports[i].enable = utrue;
      conf->sports[i].enable_sec = ufalse;
      conf->sports[i].lfs = ufalse;
      conf->sports[i].mfd = 1;
      conf->sports[i].opmode = 0 ; //tdm
      conf->sports[i].lfs = ufalse;   // The USB left and right channels can be swapped.
      conf->sports[i].mfd = 0;
      conf->sports[i].opmode = 1 ; //i2s
      conf->sports[i].rx = ufalse;
      conf->sports[i].slots = 8;
      conf->sports[i].vld = 8;
      conf->sports[i].slots = 2;
      conf->sports[i].vld = 2;
      conf->sports[i].follow_intr_no = intr_sport_no(4);
   }
   conf->sports[4].interrupt = utrue;
@@ -114,27 +126,100 @@
   conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
   conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
   AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
   // route
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_AFS_I);
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_BFS_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_ACLK_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_BCLK_I);

   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN09_I);//fs
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN08_I);//sclk
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::DAI0_PB09_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::DAI0_PB08_I);
//   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN09_I);//fs
//   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN08_I);//sclk
//   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::DAI0_PB09_I);
//   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::DAI0_PB08_I);

   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);
//   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_ACLK_I);
//   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_AFS_I);
//   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SPT2_BCLK_I);
//   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SPT2_BFS_I);

   AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I);
//   AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SPT2_AD0_I);   // usb output
//   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
//   AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I);   // usb input

   // usb asrc
   conf->srcs[0].enable = utrue;
   conf->srcs[0].format = 1;
   conf->srcs[0].wordLen = 0;
   conf->srcs[0].ratio = 1;   // usb input

   conf->srcs[1].enable = utrue;
   conf->srcs[1].format = 1;
   conf->srcs[1].wordLen = 0;
   conf->srcs[1].ratio = 0;   // usb output

   // usb input / asrc input
   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC0_FS_IP_I);
   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC0_CLK_IP_I);
   AddRoute(SourceSignal::DAI0_PB07_O, DestSignal::SRC0_DAT_IP_I);
   // usb input / asrc output
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC0_FS_OP_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC0_CLK_OP_I);
   AddRoute(SourceSignal::SRC0_DAT_OP_O, DestSignal::SPT2_AD0_I);
   // usb output / asrc input
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SRC1_FS_IP_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SRC1_CLK_IP_I);
   AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::SRC1_DAT_IP_I);
   // usb output / asrc output
   AddRoute(SourceSignal::DAI0_PB09_O, DestSignal::SRC1_FS_OP_I);
   AddRoute(SourceSignal::DAI0_PB08_O, DestSignal::SRC1_CLK_OP_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN10_I);
   AddRoute(SourceSignal::SPT2_BD0_O, DestSignal::DAI0_PB10_I);
   AddRoute(SourceSignal::SRC1_DAT_OP_O, DestSignal::DAI0_PB10_I);

   //Dante。
   //Dante Slave
   //MCLK(DAI1_2),LRCLK(DAI1_20),SCLK(DAI1_19)
   //RX0(DAI1_12),RX1(DAI1_10),RX2(DAI1_8),RX3(DAI1_6)
   //TX0(DAI1_11),TX1(DAI1_9),TX2(DAI1_7),TX3(DAI1_5)
   //TX0(DAI1_12),TX1(DAI1_10),TX2(DAI1_8),TX3(DAI1_6)
   //RX0(DAI1_11),RX1(DAI1_9),RX2(DAI1_7),RX3(DAI1_5)
   //sport4a,4b<->RX;sport5a,5b<->TX
   for(i = 8 ;i < 12 ;i ++) {
         conf->sports[i].spid = i;
         conf->sports[i].clke = utrue;
         conf->sports[i].enable = utrue;
         conf->sports[i].enable_sec = ufalse;
         conf->sports[i].lfs = ufalse;
         conf->sports[i].mfd = 1;
         conf->sports[i].opmode = 0 ; //tdm
         conf->sports[i].rx = ufalse;
         conf->sports[i].slots = 8;
         conf->sports[i].vld = 8;
         conf->sports[i].follow_intr_no = intr_sport_no(8);
      }
      conf->sports[8].interrupt = utrue;
      conf->sports[8].rx = conf->sports[9].rx = utrue;

      AddRoute(SourceSignal::DAI1_PB19_O, DestSignal::SPT4_ACLK_I);
      AddRoute(SourceSignal::DAI1_PB19_O, DestSignal::SPT4_BCLK_I);
      AddRoute(SourceSignal::DAI1_PB19_O, DestSignal::SPT5_ACLK_I);
      AddRoute(SourceSignal::DAI1_PB19_O, DestSignal::SPT5_BCLK_I);
      AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT4_AFS_I);
      AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT4_BFS_I);
      AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT5_AFS_I);
      AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT5_BFS_I);

      AddRoute(SourceSignal::DAI1_PB11_O, DestSignal::SPT4_AD0_I);
      AddRoute(SourceSignal::DAI1_PB09_O, DestSignal::SPT4_BD0_I);
//      AddRoute(SourceSignal::DAI1_PB07_O, DestSignal::SPT4_AD0_I);
//      AddRoute(SourceSignal::DAI1_PB05_O, DestSignal::SPT4_BD0_I);

      AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN12_I);
      AddRoute(SourceSignal::SPT5_AD0_O, DestSignal::DAI1_PB12_I);
      AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN10_I);
      AddRoute(SourceSignal::SPT5_BD0_O, DestSignal::DAI1_PB10_I);
//      AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN08_I);
//      AddRoute(SourceSignal::SPT5_AD0_O, DestSignal::DAI1_PB08_I);
//      AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN06_I);
//      AddRoute(SourceSignal::SPT5_BD0_O, DestSignal::DAI1_PB06_I);
   /* TDM8
       for(i = 8 ;i < 12 ;i ++) {
      conf->sports[i].spid = i;
      conf->sports[i].clke = utrue;
      conf->sports[i].enable = utrue;
@@ -159,17 +244,17 @@
   AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT5_AFS_I);
   AddRoute(SourceSignal::DAI1_PB20_O, DestSignal::SPT5_BFS_I);

   AddRoute(SourceSignal::DAI1_PB12_O, DestSignal::SPT4_AD0_I);
   AddRoute(SourceSignal::DAI1_PB10_O, DestSignal::SPT4_AD1_I);
   AddRoute(SourceSignal::DAI1_PB08_O, DestSignal::SPT4_BD0_I);
   AddRoute(SourceSignal::DAI1_PB06_O, DestSignal::SPT4_BD1_I);
   AddRoute(SourceSignal::DAI1_PB11_O, DestSignal::SPT4_AD0_I);
   AddRoute(SourceSignal::DAI1_PB09_O, DestSignal::SPT4_AD1_I);
   AddRoute(SourceSignal::DAI1_PB07_O, DestSignal::SPT4_BD0_I);
   AddRoute(SourceSignal::DAI1_PB05_O, DestSignal::SPT4_BD1_I);

   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN11_I);
   AddRoute(SourceSignal::SPT5_AD0_O, DestSignal::DAI1_PB11_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN09_I);
   AddRoute(SourceSignal::SPT5_AD1_O, DestSignal::DAI1_PB09_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN07_I);
   AddRoute(SourceSignal::SPT5_BD0_O, DestSignal::DAI1_PB07_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN05_I);
   AddRoute(SourceSignal::SPT5_BD1_O, DestSignal::DAI1_PB05_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN12_I);
   AddRoute(SourceSignal::SPT5_AD0_O, DestSignal::DAI1_PB12_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN10_I);
   AddRoute(SourceSignal::SPT5_AD1_O, DestSignal::DAI1_PB10_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN08_I);
   AddRoute(SourceSignal::SPT5_BD0_O, DestSignal::DAI1_PB08_I);
   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI1_PBEN06_I);
   AddRoute(SourceSignal::SPT5_BD1_O, DestSignal::DAI1_PB06_I);*/
}