| | |
| | | #include <stdint.h> |
| | | #include <stdio.h> |
| | | #include <services/int/adi_int.h> |
| | | #include <services/int/adi_sec.h> |
| | | #include <drivers/spi/adi_spi.h> |
| | | #include <signal.h> |
| | | #include "typedefs.h" |
| | | #include "spi.h" |
| | | #include "gpio.h" |
| | | #include "config.h" |
| | | #include <drivers/spi/adi_spi.h> |
| | | |
| | | |
| | | #define MASTER 0 |
| | | #define CPHA 1 |
| | |
| | | |
| | | // GPIO_SetOutPut(GPIOA, GPIO_Pin12|GPIO_Pin13, GPIO_HIGH); |
| | | // GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_HIGH); |
| | | GPIO_SetOutPut(GPIOA, GPIO_Pin13, GPIO_LOW); |
| | | GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_LOW); |
| | | |
| | | SPIRxCnt ++ ; |
| | | SPIRxDone = 1; |
| | |
| | | *pREG_DMA26_CFG = (MSIZE<<8) | (PSIZE<<4) | 4 ; |
| | | *pREG_DMA26_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA26_XMOD = 1; |
| | | *pREG_DMA26_ADDRSTART= (uint32_t)SPI_Tx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA26_ADDRSTART= (void *)((uint32_t)SPI_Tx_BUFFER|MP_OFFSET); |
| | | *pREG_DMA26_CFG |= 1 ; |
| | | |
| | | *pREG_SPI2_TXCTL |= (1<<0); |
| | |
| | | *pREG_DMA27_CFG = (1<<1)| (MSIZE<<8) | (PSIZE<<4) | (1<<20) | 4 ; |
| | | *pREG_DMA27_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA27_XMOD = 1; |
| | | *pREG_DMA27_ADDRSTART= (uint32_t)SPI_Rx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA27_ADDRSTART= (void *)((uint32_t)SPI_Rx_BUFFER|MP_OFFSET); |
| | | *pREG_DMA27_CFG |= 1 ; |
| | | |
| | | *pREG_SPI2_RXCTL |= (1<<0); |
| | |
| | | *pREG_DMA26_CFG = (MSIZE<<8) | (PSIZE<<4) | 4 ; |
| | | *pREG_DMA26_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA26_XMOD = 1; |
| | | *pREG_DMA26_ADDRSTART= (uint32_t)SPI_Tx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA26_ADDRSTART= (void *)((uint32_t)SPI_Tx_BUFFER|MP_OFFSET); |
| | | *pREG_DMA26_CFG |= 1 ; |
| | | |
| | | *pREG_DMA27_CFG = (1<<1)| (MSIZE<<8) | (PSIZE<<4) | (1<<20) | 4 ; |
| | | *pREG_DMA27_XCNT = SPI_BUFFER_SIZE; |
| | | *pREG_DMA27_XMOD = 1; |
| | | *pREG_DMA27_ADDRSTART= (uint32_t)SPI_Rx_BUFFER|MP_OFFSET; |
| | | *pREG_DMA27_ADDRSTART= (void *)((uint32_t)SPI_Rx_BUFFER|MP_OFFSET); |
| | | *pREG_DMA27_CFG |= 1 ; |
| | | |
| | | *pREG_SPI2_CTL= (MASTER<<1)|(0<<3)|(CPHA<<4)|(CPOL<<5)|(1<<6)|(1<<8)|(BITS<<9)|(1<<0); |