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chenlh

2025-09-18 8445c54f01777513912d4c6d36c28e92a0ff33a0

 src/tg/tg_adapter.cpp

@@ -2,8 +2,10 @@
#include "tg_config.h"
#include "tg_adapter.h"

//参数logic_channel逻辑通道从0开始.
s32 tg_hw_adapter_t::get_physical_channel(s32 input , s32 logic_channel)
{
<<<<<<< HEAD
    if(input) {
        s32 input_num = ana_input_num + dante_input_num ;
        if(logic_channel < ana_input_num) {
@@ -36,6 +38,41 @@
           return (logic_channel > output_num) ? 17 : 18;
        }
    }
=======
   //s32 phy_channel[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,19};
   if(input) {
      s32 input_num = ana_input_num + dante_input_num ;
//      s32 local_ch = ana_input_num + usb_input_num;   // C H G 18
      if(logic_channel < ana_input_num) {
         //analog
         return logic_channel+1;
      }
      else if(logic_channel < input_num) {
         //dante
         return 19 + (logic_channel - ana_input_num);
      }
      else {
         //usb
         return 17 + (logic_channel - input_num);
      }
   }
   else {   //output
      s32 output_num = ana_output_num + dante_output_num ;
//      s32 local_ch = ana_output_num + usb_output_num;   // C H G 18
      //analog
      if(logic_channel < ana_output_num) {
         return logic_channel;
      }
      else if(logic_channel < output_num) {
         //dante
         return 19 + (logic_channel - ana_output_num);
      }
      else {
         //usb
         return 17 + (logic_channel - output_num);
      }
   }
>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
}

//物理buffer定义顺序是16通道模拟+2通道USB+32通道Dante.
@@ -109,8 +146,13 @@
      conf->sports[i].clke = utrue;
      conf->sports[i].enable = utrue;
      conf->sports[i].enable_sec = ufalse;
<<<<<<< HEAD
      conf->sports[i].lfs = ufalse;   // The USB left and right channels can be swapped.
      conf->sports[i].mfd = 0;
=======
      conf->sports[i].lfs = ufalse;
      conf->sports[i].mfd = 1;
>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
      conf->sports[i].opmode = 1 ; //i2s
      conf->sports[i].rx = ufalse;
      conf->sports[i].slots = 2;
@@ -121,6 +163,7 @@
   conf->sports[4].rx = utrue;

   //USB pcg.
<<<<<<< HEAD
   conf->pcgs[1].enable = utrue;
   conf->pcgs[1].opmode = 0;
   conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
@@ -131,6 +174,13 @@
   AddRoute(SourceSignal::PCG_FSB_O, DestSignal::SPT2_BFS_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_ACLK_I);
   AddRoute(SourceSignal::PCG_CLKB_O, DestSignal::SPT2_BCLK_I);
=======
//   conf->pcgs[1].enable = utrue;
//   conf->pcgs[1].opmode = 0;
//   conf->pcgs[1].fs_div = mclk / conf->mSampleRate ;
//   conf->pcgs[1].sclk_div = mclk / (conf->mSampleRate * 2 * 32);
//   AddRoute(SourceSignal::DAI0_PB02_O, DestSignal::PCG_EXTB_I);
>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430

//   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN09_I);//fs
//   AddRoute(SourceSignal::LOGIC_HIGH, DestSignal::DAI0_PBEN08_I);//sclk
@@ -189,8 +239,13 @@
         conf->sports[i].mfd = 1;
         conf->sports[i].opmode = 0 ; //tdm
         conf->sports[i].rx = ufalse;
<<<<<<< HEAD
         conf->sports[i].slots = 8;
         conf->sports[i].vld = 8;
=======
         conf->sports[i].slots = 16;
         conf->sports[i].vld = 16;
>>>>>>> 0d5b7df96a2ee186b7b085dca9cf9a33f791c430
         conf->sports[i].follow_intr_no = intr_sport_no(8);
      }
      conf->sports[8].interrupt = utrue;