/*
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** ADSP-21569 startup code generated on Aug 02, 2023 at 21:46:12.
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*/
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/*
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** Copyright (C) 2000-2022 Analog Devices Inc., All Rights Reserved.
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**
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** This file is generated automatically based upon the options selected
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** in the System Configuration utility. Changes to the Startup Code configuration
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** should be made by modifying the appropriate options rather than editing
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** this file. To access the System Configuration utility, double-click the
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** system.svc file from a navigation view.
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**
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** Custom additions can be inserted within the user-modifiable sections. These
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** sections are bounded by comments that start with "$VDSG". Only changes
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** placed within these sections are preserved when this file is re-generated.
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**
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** Product : CrossCore Embedded Studio
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** Tool Version : 6.2.3.3
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*/
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.FILE_ATTR libGroup="startup";
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.FILE_ATTR libName="libc";
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.FILE_ATTR libFunc="___lib_prog_term";
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.FILE_ATTR FuncName="___lib_prog_term";
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.FILE_ATTR libFunc="start";
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.FILE_ATTR FuncName="start";
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.FILE_ATTR prefersMem="any";
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.FILE_ATTR prefersMemNum="50";
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#include <sys/anomaly_macros_rtl.h> // defines silicon anomaly macros
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#include <interrupt.h> // defines interrupt support
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#include <platform_include.h> // defines MMR macros
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#include <adi_osal.h> // OSAL support
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#include <sys/fatal_error_code.h> // defines fatal error support
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/* End marker for the list of static constructors.
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** seg_ctdml has to be mapped right after seg_ctdm.
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*/
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.SECTION/DATA/DOUBLEANY seg_ctdml;
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.RETAIN_NAME __ctor_NULL_marker;
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.GLOBAL __ctor_NULL_marker;
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.VAR __ctor_NULL_marker = 0;
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/* The .gdt (global dispatch table) data is used by the C++ exception
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** runtime library support to determine which area of code a particular
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** exception belongs. These .gdt sections must be mapped to contiguous
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** memory by the LDF starting with this one and and ending with .gdtl.
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** The word addressed variants of these sections also need to be included
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** and are called .gdt32 and .gdtl32.
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*/
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.SECTION/DOUBLEANY .gdt;
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.ALIGN 4;
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.BYTE __eh_gdt.[4];
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.GLOBAL __eh_gdt.;
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.TYPE __eh_gdt.,STT_OBJECT;
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.SECTION/DM/DOUBLEANY .gdt32;
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.VAR ___eh_gdt[1];
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.GLOBAL ___eh_gdt;
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.TYPE ___eh_gdt,STT_OBJECT;
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/* Suppress the assemblers informational message regarding the automatic
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** call sequence change it does when building -swc.
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*/
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.MESSAGE/SUPPRESS 2536;
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.GLOBAL start;
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.SECTION/CODE/DOUBLEANY seg_pmco;
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start:
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/* Disable the BTB. */
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R0 = DM(REG_SHBTB0_CFG); /* Get current BTB configuration. */
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R0 = BSET R0 BY BITP_SHBTB_CFG_DIS; /* Disable the BTB */
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DM(REG_SHBTB0_CFG) = R0; /* Write back to BTB_CFG MMR. */
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/* After a write to the SHBTB_CFG register there must be at least
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** 12 48-bit (ISA) instructions, which do not involve any change
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** of flow.
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*/
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.NOCOMPRESS;
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NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
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.COMPRESS;
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/* Ensure caches are disabled - enables a soft reset to jump to start
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** and also avoids problems if a preload enables caches.
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*/
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/* Cache configuration updates only while executing in L1 memory. */
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R0 = 0;
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JUMP (.disable_caches);
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.SECTION/SW/DOUBLEANY seg_int_code;
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.disable_caches:
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DM(REG_SHL1C0_CFG) = R0;
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/* 12 uncompressed NOPs after a cache MMR access. */
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.NOCOMPRESS;
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NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
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.COMPRESS;
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JUMP (.caches_disabled);
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.PREVIOUS;
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.caches_disabled:
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/* Enable instruction, data and system transfer parity checking for
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** parts and revisions that have all required support. The ADSP-SC58x
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** and ADSP-2158x revisions 0.0 and 0.1 system reset does not work and
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** this is required so we don't enable parity for these.
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*/
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#if !defined(__IS_FPGA__) && \
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(!defined(__ADSPSC589_FAMILY__) || \
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(!defined(__SILICON_REVISION__) || \
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((__SILICON_REVISION__ >= 0x0100) && (__SILICON_REVISION__ != 0xFFFF))))
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BIT SET MODE1 (BITM_REGF_MODE1_IPERREN | BITM_REGF_MODE1_DPERREN |
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BITM_REGF_MODE1_SPERREN );
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/* Wait 11 cycles for the change to take effect. */
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NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
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#define ENABLED_PARITY_ERROR_CHECKING
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#else
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/* Explicitly disable parity error checking when we don't enable it
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** for the application. This may be necessary for ADSP-215xx (non-ARM)
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** parts as the SHARC+ boot can enable parity error checking.
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*/
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BIT CLR MODE1 (BITM_REGF_MODE1_IPERREN | BITM_REGF_MODE1_DPERREN |
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BITM_REGF_MODE1_SPERREN );
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/* Wait 11 cycles for the change to take effect. */
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NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
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#endif
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/* Zero all the BTB memory locations to initialize the parity bits. */
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I0 = 0x31000;
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L0 = 0;
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M0 = 1;
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R0 = 0;
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LCNTR = 0x400, DO (PC,.BTB_init_loop) UNTIL LCE;
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.BTB_init_loop:
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DM(I0, M0) = R0;
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/* Also zero the L1 cache memory locations... **/
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/* ... Icache tag */
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I0 = 0x3E400;
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LCNTR = 0x400, DO (PC,.icache_tag_loop) UNTIL LCE;
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.icache_tag_loop:
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DM(I0, M0) = R0;
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/* ... then dcache (dmcache + pmcache) tag */
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I0 = 0x3C000;
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LCNTR = 0x1000, DO (PC,.dcache_tag_loop) UNTIL LCE;
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.dcache_tag_loop:
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DM(I0, M0) = R0;
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/* ... then dmcache LRU/DIRTY */
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I0 = 0x3D100;
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LCNTR = 0x100, DO (PC,.dmcache_dirty_loop) UNTIL LCE;
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.dmcache_dirty_loop:
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DM(I0, M0) = R0;
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/* ... then pmcache LRU/DIRTY */
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I0 = 0x3D300;
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LCNTR = 0x100, DO (PC,.pmcache_dirty_loop) UNTIL LCE;
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.pmcache_dirty_loop:
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DM(I0, M0) = R0;
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/* ... then icache LRU/DIRTY */
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I0 = 0x3d500;
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LCNTR = 0x80, DO (PC,.icache_dirty_loop) UNTIL LCE;
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.icache_dirty_loop:
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DM(I0, M0) = R0;
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R0 = DM(REG_SHBTB0_CFG); /* Get current BTB configuration. */
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R0 = BCLR R0 BY BITP_SHBTB_CFG_DIS; /* Enable the BTB */
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R0 = BSET R0 BY BITP_SHBTB_CFG_INVAL; /* Invalidate the BTB */
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/* Turn off software return prediction in the BTB, because we can't
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** guarantee i12 has a valid code address, and a speculative access
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** to an invalid address can cause a hardware error.
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*/
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R0 = BSET R0 BY BITP_SHBTB_CFG_SRETDIS; /* Software return disable. */
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DM(REG_SHBTB0_CFG) = R0; /* Write back to BTB_CFG MMR. */
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/* After a write to the SHBTB_CFG register there must be at least
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** 12 48-bit (ISA) instructions, which do not involve any change of
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** flow.
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*/
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.NOCOMPRESS;
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NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
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.COMPRESS;
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/* There might be entries on the loop, PC and status stacks. Clear them all.
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** First, clear the loop stack.
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*/
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BIT TST STKY BITM_REGF_STKYX_LSEM;
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.pop_loop_stack:
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IF TF JUMP (PC, .loop_stack_empty);
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JUMP (PC, .pop_loop_stack) (DB);
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POP LOOP;
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BIT TST STKY BITM_REGF_STKYX_LSEM;
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.loop_stack_empty:
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/* Then, clear the status stack. */
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BIT TST STKY BITM_REGF_STKYX_SSEM;
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.pop_status_stack:
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IF TF JUMP (PC, .status_stack_empty);
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JUMP (PC, .pop_status_stack) (DB);
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POP STS;
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BIT TST STKY BITM_REGF_STKYX_SSEM;
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.status_stack_empty:
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/* Then clear the PC stack. PC stack cannot be popped in a delay slot. */
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.pop_pc_stack:
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BIT TST STKY BITM_REGF_STKYX_PCEM;
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IF TF JUMP (PC, .pc_stack_empty);
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POP PCSTK;
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JUMP (PC, .pop_pc_stack);
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.pc_stack_empty:
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/* Set the vector register to 'start' so that if the processor
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** is reset the processor bypasses the boot ROM code.
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*/
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R0 = start;
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DM(REG_RCU0_SVECT0) = R0;
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/*$VDSG<insert-code-very-beginning> */
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.start_of_user_code_very_beginning:
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/*
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** Insert any additional code to be executed before any other
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** startup code here.
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** Code inserted here is preserved when this file is re-generated.
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** Note that the C runtime environment hasn't been set up yet
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** so you cannot call C or C++ functions.
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*/
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.end_of_user_code_very_beginning:
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/*$VDSG<insert-code-very-beginning> */
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/*
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** Initializes the processor, memory, C runtime and heaps.
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*/
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.EXTERN ___lib_setup_c;
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CALL ___lib_setup_c;
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/*$VDSG<insert-code-after-setup> */
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.start_of_user_code_after_setup:
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/*
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** Insert any additional code to be executed at the start after
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** the C runtime and hardware has been initialized.
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** Code inserted here is preserved when this file is re-generated.
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*/
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.end_of_user_code_after_setup:
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/*$VDSG<insert-code-after-setup> */
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/*
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** Enable the ILOPI interrupt to support illegal opcode detection.
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** The interrupt vector code for Illegal Opcode detection
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** jumps directly to stub handler _adi_ilop_detected.
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*/
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.EXTERN adi_rtl_activate_dispatched_handler.;
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R4 = ADI_CID_ILOPI;
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CJUMP adi_rtl_activate_dispatched_handler. (DB);
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DM(I7, M7) = R2;
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DM(I7, M7) = PC;
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#if defined(ENABLED_PARITY_ERROR_CHECKING)
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/*
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** Enable the PARI interrupt to support L1 parity error detection.
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** The interrupt vector code for this interrupt jumps directly
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** to stub handler _adi_parity_error_detected.
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*/
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.EXTERN adi_rtl_activate_dispatched_handler.;
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R4 = ADI_CID_PARI;
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CJUMP adi_rtl_activate_dispatched_handler. (DB);
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DM(I7, M7) = R2;
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DM(I7, M7) = PC;
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#endif
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/*
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** Call the OSAL init function.
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*/
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.EXTERN adi_osal_Init.; // ADI_OSAL_STATUS adi_osal_Init(void);
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CJUMP adi_osal_Init. (DB);
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DM(I7, M7) = R2;
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DM(I7, M7) = PC;
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R1 = E_ADI_OSAL_SUCCESS;
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COMPU(R0, R1);
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IF NE JUMP .osal_Init_failed;
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/*
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** Call all the byte-addressed then word-addressed C++ static
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** class instance constructors.
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*/
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.EXTERN __ctors, _ctors.; // defined in the LDF file
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I0 = _ctors.; // load pointer to the list of constructors
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// for byte addressing into call preserved I0
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R15 = 2; // counter held in R15
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R5 = I6; // hold current I6 in preserved register R5
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.call_ctors_start:
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R0 = DM(I0, M6); // get the address of the first constructor
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R0 = PASS R0, I13 = R0; // check if it's the NULL list terminator
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.call_ctors:
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IF EQ JUMP (PC, .call_ctors_next); // if NULL we found the list end
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I6 = I7;
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JUMP (M13, I13) (DB); // call the constructor
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DM(I7, M7) = R5;
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DM(I7, M7) = PC;
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JUMP (PC, .call_ctors) (DB);
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R0 = DM(I0, M6); // get the address of the next constructor
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R0 = PASS R0, I13 = R0; // check if it's the NULL list terminator
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.call_ctors_next:
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R15 = R15 - 1; // decrement counter
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If EQ JUMP (PC, .call_ctors_exit);
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I0 = __ctors; // word-addressing constructors list
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I7 = B2W(I7);
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B7 = B2W(B7);
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JUMP (PC, .call_ctors_start) (DB);
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I6 = B2W(I6);
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B6 = B2W(B6);
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.call_ctors_exit:
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/*
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** Transform back to byte-addressed frame.
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*/
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I7 = W2B(I7);
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B7 = W2B(B7);
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I6 = W2B(I6);
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B6 = W2B(B6);
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R4 = R4 - R4, // argc = 0
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R8 = M5; // argv = NULL
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/*$VDSG<insert-code-before-call-to-main> */
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.start_of_user_code1:
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/*
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** Insert any additional code to be executed before calling main() here.
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** Code inserted here is preserved when this file is re-generated.
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** Avoid clobbering the values of registers R4 and R8 as they hold
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** the argc and argv parameters for main().
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*/
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.end_of_start_of_user_code1:
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/*$VDSG<insert-code-before-call-to-main> */
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.EXTERN main.;
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JUMP main. (DB); // call main()
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DM(I7, M7) = 0; // NULL FP to terminate call stack unwinding
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DM(I7, M7) = ___lib_prog_term-1;
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.start.end:
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.GLOBAL ___lib_prog_term;
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___lib_prog_term: // Automatic breakpoint location.
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NOP; // Placed prior to loop label so that we
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// break only once.
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.lib_prog_term_loop:
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IDLE;
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JUMP .lib_prog_term_loop; // Stay put.
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.___lib_prog_term.end:
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/*
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** The call to _adi_osal_Init returned an error so call _adi_fatal_error.
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*/
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.EXTERN adi_fatal_error.;
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.osal_Init_failed:
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R12 = R0; // pass adi_osal_Init result value
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JUMP adi_fatal_error. (DB); // doesn't return
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R4 = _AFE_G_LibraryError;
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R8 = _AFE_S_adi_osal_Init_failure;
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.osal_Init_failed.end:
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