/*
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* board.c
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*
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* Created on: 2021Äê9ÔÂ1ÈÕ
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* Author: graydon
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*/
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#include <stdio.h>
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#include <services/int/adi_int.h>
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#include <services/spu/adi_spu.h>
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#include <services/pwr/adi_pwr.h>
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#include <services/gpio/adi_gpio.h>
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#include <SRU.h>
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#include "DMCInit.h"
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#include "board.h"
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#include "gpio.h"
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#include "config.h"
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#include "ddr_sweep.h"
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#include "sport.h"
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void spu_config(void)
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{
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*pREG_SPU0_SECUREP32= 0x3; //PORTA
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*pREG_SPU0_SECUREP33= 0x3; //PORTB
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*pREG_SPU0_SECUREP34= 0x3; //PORTC
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*pREG_SPU0_SECUREP81= 0x3;//BITM_SPU_SECUREP_MSEC; //spi2
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*pREG_SPU0_SECUREP77= 0x3; //SPI2 TX DMA26
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*pREG_SPU0_SECUREP78= 0x3; //SPI2 RX DMA27
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//sport0-8 AB.
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*pREG_SPU0_SECUREP13= 0x3;
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*pREG_SPU0_SECUREP14= 0x3;
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*pREG_SPU0_SECUREP15= 0x3;
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*pREG_SPU0_SECUREP16= 0x3;
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*pREG_SPU0_SECUREP17= 0x3;
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*pREG_SPU0_SECUREP18= 0x3;
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*pREG_SPU0_SECUREP19= 0x3;
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*pREG_SPU0_SECUREP20= 0x3;
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*pREG_SPU0_SECUREP21= 0x3;
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*pREG_SPU0_SECUREP22= 0x3;
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*pREG_SPU0_SECUREP23= 0x3;
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*pREG_SPU0_SECUREP24= 0x3;
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*pREG_SPU0_SECUREP25= 0x3;
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*pREG_SPU0_SECUREP26= 0x3;
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*pREG_SPU0_SECUREP27= 0x3;
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*pREG_SPU0_SECUREP28= 0x3;
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//sport dma 0-7 ab
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*pREG_SPU0_SECUREP49= 0x3;
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*pREG_SPU0_SECUREP50= 0x3;
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*pREG_SPU0_SECUREP51= 0x3;
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*pREG_SPU0_SECUREP52= 0x3;
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*pREG_SPU0_SECUREP53= 0x3;
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*pREG_SPU0_SECUREP54= 0x3;
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*pREG_SPU0_SECUREP55= 0x3;
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*pREG_SPU0_SECUREP56= 0x3;
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*pREG_SPU0_SECUREP57= 0x3;
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*pREG_SPU0_SECUREP58= 0x3;
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*pREG_SPU0_SECUREP59= 0x3;
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*pREG_SPU0_SECUREP60= 0x3;
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*pREG_SPU0_SECUREP61= 0x3;
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*pREG_SPU0_SECUREP62= 0x3;
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*pREG_SPU0_SECUREP63= 0x3;
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*pREG_SPU0_SECUREP64= 0x3;
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}
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void pinmux_config(void)
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{
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int i ,j ;
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//led
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GPIO_Init(GPIOC, GPIO_Pin0, MODE_0);
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GPIO_Set_Direction(GPIOC, GPIO_Pin0,GPIO_OUT);
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//aec card led.
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GPIO_Init(GPIOB, GPIO_Pin10, MODE_0);
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GPIO_Set_Direction(GPIOB, GPIO_Pin10,GPIO_OUT);
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//spi
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GPIO_Init(GPIOA, GPIO_Pin0|GPIO_Pin1|GPIO_Pin4|GPIO_Pin5, MODE_1);
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//ÀúÊ·ÒÅÁôÔÒòÒÔÇ°µÄ°å¿¨IO½ÅûÓÐͳһ£¬ÐèÒª¶ÔÒÔÇ°°æ±¾GPIO_Pin12 Ö§³Ö for tx.¡£
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//GPIOA_Pin13 ---- rx. busy ..
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//GPIOB_Pin5,GPIO_Pin12 ---- tx. dir.
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//dir, 0-tx,1-rx.
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//busy:0-no busy,1 -busy
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//for AEC Card..
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GPIO_Init(GPIOA, GPIO_Pin12|GPIO_Pin13, MODE_0); //io for tx.
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GPIO_Init(GPIOB, GPIO_Pin5, MODE_0); //for rx
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GPIO_Set_Direction(GPIOA, GPIO_Pin12 | GPIO_Pin13,GPIO_OUT);
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GPIO_Set_Direction(GPIOB, GPIO_Pin5,GPIO_OUT);
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GPIO_SetOutPut(GPIOA, GPIO_Pin12, GPIO_HIGH);
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GPIO_SetOutPut(GPIOA, GPIO_Pin13, GPIO_HIGH);
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GPIO_SetOutPut(GPIOB, GPIO_Pin5, GPIO_HIGH);
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//for main board..
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//io 4 for tx(dir), io 7 for rx(busy). high can not rx or tx. low allowed.
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GPIO_Init(GPIOC, GPIO_Pin4|GPIO_Pin7, MODE_0);
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GPIO_Set_Direction(GPIOC, GPIO_Pin4|GPIO_Pin7,GPIO_OUT);
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GPIO_SetOutPut(GPIOC, GPIO_Pin4|GPIO_Pin7, GPIO_HIGH);
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//quick blink led.
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for(i =0 ; i< 3; i++) {
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GPIO_SetOutPut(GPIOC, GPIO_Pin0, GPIO_HIGH);
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GPIO_SetOutPut(GPIOB, GPIO_Pin10, GPIO_HIGH);//V2
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for(j = 0;j<4000000;j++) asm("nop;") ;
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GPIO_SetOutPut(GPIOC, GPIO_Pin0, GPIO_LOW);
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GPIO_SetOutPut(GPIOB, GPIO_Pin10, GPIO_LOW);
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for(j = 0;j<4000000;j++) asm("nop;") ;
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}
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}
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/*
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* CGU0: SYSCLK0,SCLK0,CCLK0,SCLK1,OCLK0,DCLK0
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* cclk : core clock frequency
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* SYSCLK0 : System, L2 mem/cache, SEC High speed peripherals
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* SCLK0 :Peripherals
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* SCLK0/OCLK0 : SPI SOURCE CLOCK
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* SCLK1 : SPDIF RX CLOCK
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* DCLK0 -DCLK1: DDR CLOCK ,
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* DCLK derived from CGU0..DCLK frequency = (SYS_CLKIN frequency/(DF+1)) MSEL/CGU_DIV.DSEL
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* SYS_CLKIN = 25M. DF:0, MSEL: 80
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* CGU1:
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* DCLK1 : DDR CLOCK,DCLK derived from CGU1
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*/
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int DDR_config()
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{
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extern uint32_t adi_pwr_cfg0_init(void);
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//cgu_init();
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adi_pwr_Init(0, 25000000);
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adi_pwr_cfg0_init();
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uint32_t cclk,sclk,sclk0,sclk1,dclk,oclk;
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adi_pwr_GetCoreClkFreq(0, &cclk);
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adi_pwr_GetSystemFreq(0, &sclk, &sclk0, &sclk1);
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adi_pwr_GetDDRClkFreq(0, &dclk);
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adi_pwr_GetOutClkFreq(0, &oclk);
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if(dmc_cfg0_init() > 0){
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return -1;
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}
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//256MB.
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//if(Memory_Sweep_Test(0x80000000, 0x10000000)>0){
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if(Memory_Sweep_Test(0x80000000, 0x100000)>0){
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return -1;
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}
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return 0;
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}
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void SportsConfig(struct SportDef sports[8])
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{
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u32 i ;
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for(i =0 ;i < 16 ;i ++) {
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if(sports[i].enable && sports[i].spid < 16) {
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if(sports[i].interrupt) {
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dma_install_interrupt(sports[i].spid);
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}
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sport_config(get_sport_regs(sports[i].spid) , &sports[i]);
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}
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}
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for(i =0 ;i < 16 ;i ++) {
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if(sports[i].enable && sports[i].spid < 16) {
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dma_enable(get_dma_regs(sports[i].spid));
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sport_enable(get_sport_regs(sports[i].spid), sports[i].enable_sec);
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}
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}
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}
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void RouteConfig(struct RouteDef* items, u32 nItems)
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{
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u32 i ;
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for(i = 0 ;i < nItems ;i++) {
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dai_route(items[i].source, items[i].dest);
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}
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}
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void PCGsConfig(struct PCGDef pcgs[4])
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{
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u32 i;
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volatile u32* pcg_pw[4] = {pREG_PCG0_PW1, pREG_PCG0_PW1 ,pREG_PCG0_PW2 ,pREG_PCG0_PW2};
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volatile u32* pcg_ctlc0[4] = {pREG_PCG0_CTLA0, pREG_PCG0_CTLB0 ,pREG_PCG0_CTLC0 ,pREG_PCG0_CTLD0};
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volatile u32* pcg_ctlc1[4] = {pREG_PCG0_CTLA1, pREG_PCG0_CTLB1 ,pREG_PCG0_CTLC1 ,pREG_PCG0_CTLD1};
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*pREG_PCG0_PW1 = 0; *pREG_PCG0_PW1 = 0;
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for(i = 0; i < 4; i++) {
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if (pcgs[i].enable ) {
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s32 n,r0 ;
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*pcg_ctlc1[i] =0 ; *pcg_ctlc0[i] =0;
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for (n=0; n<16; n++)asm("NOP;");
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if(pcgs[i].opmode) {
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if(pcgs[i].fs_div > 0) {
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*pcg_pw[i] |= (i&0x1)?(pcgs[i].width<<16):pcgs[i].width;
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}
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else if(pcgs[i].invert){
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//bypass mode.
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*pcg_pw[i] |= (i&0x1)?(1<<17):(1<<1);
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}
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r0 = pcgs[i].sclk_div| (1<<30) | (1<<31) ;
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}
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else {
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r0 = pcgs[i].sclk_div| (1<<30) | (1<<31) | ((pcgs[i].sclk_div/2)<<20);
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}
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*pcg_ctlc1[i] = r0 ;
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r0 = pcgs[i].fs_div | (1<<30) | (1<<31) ;
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*pcg_ctlc0[i] = r0;
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}
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}
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}
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void SRCsConfig(int group , struct SRCDef src[8])
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{
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u32 reg[4] = {0 ,0, 0, 0};
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for(u32 i = 0 ;i < 4 ;i ++) {
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if(src[i].enable) {
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switch (src[i].format) {
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case 0:
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break;
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case 1:
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//iis
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reg[i] = (1<<2) | (1<<10) | (1<<15);
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break;
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case 2:
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//tdm
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reg[i] = (2<<2) | (2<<10) | (1<<15);
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break;
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case 3:
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break;
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}
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}
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}
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if(group) {
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*pREG_ASRC1_CTL01 = reg[0]|(reg[1]<<16);
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*pREG_ASRC1_CTL23 = reg[2]|(reg[3]<<16);
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}
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else {
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*pREG_ASRC0_CTL01 = reg[0]|(reg[1]<<16);
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*pREG_ASRC0_CTL23 = reg[2]|(reg[3]<<16);
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}
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}
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/*
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*
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fpga dai0_5 mclk.
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fpga daio_7 lrclk.
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fpga dai0_6 sclk.
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aec_out_i2s1 dai0_4
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aec_out_i2s2 dai0_3
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ad_i2s1 dai0_8
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ad_i2s2 dai0_9
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ref_i2s1 dai0_10
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ref_i2s2 dai0_11
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*
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*/
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void DAI_config()
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{
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/*SPORT0-3 signal can be routed using DAI0. SPORT4-7 signals can be routed using DAI1.
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detail saw datasheet page 22¨C6
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*/
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/*enable Pad registers for all the DAI input pins */
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*pREG_PADS0_DAI0_IE= BITM_PADS_DAI0_IE_VALUE;
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*pREG_PADS0_DAI1_IE= BITM_PADS_DAI1_IE_VALUE;
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SRU(LOW,DAI0_PBEN01_I);
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SRU(LOW,DAI0_PBEN02_I);
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SRU(LOW,DAI0_PBEN03_I);
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SRU(LOW,DAI0_PBEN04_I);
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SRU(LOW,DAI0_PBEN05_I);
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SRU(LOW,DAI0_PBEN06_I);
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SRU(LOW,DAI0_PBEN07_I);
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SRU(LOW,DAI0_PBEN08_I);
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SRU(LOW,DAI0_PBEN09_I);
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SRU(LOW,DAI0_PBEN10_I);
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SRU(LOW,DAI0_PBEN11_I);
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SRU(LOW,DAI0_PBEN12_I);
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SRU(LOW,DAI0_PBEN19_I);
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SRU(LOW,DAI0_PBEN20_I);
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SRU2(LOW,DAI1_PBEN01_I);
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SRU2(LOW,DAI1_PBEN02_I);
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SRU2(LOW,DAI1_PBEN03_I);
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SRU2(LOW,DAI1_PBEN04_I);
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SRU2(LOW,DAI1_PBEN05_I);
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SRU2(LOW,DAI1_PBEN06_I);
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SRU2(LOW,DAI1_PBEN07_I);
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SRU2(LOW,DAI1_PBEN08_I);
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SRU2(LOW,DAI1_PBEN09_I);
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SRU2(LOW,DAI1_PBEN10_I);
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SRU2(LOW,DAI1_PBEN11_I);
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SRU2(LOW,DAI1_PBEN12_I);
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SRU2(LOW,DAI1_PBEN19_I);
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SRU2(LOW,DAI1_PBEN20_I);
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//
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// SRU2(DAI1_CRS_PB03_O,DAI0_PB03_I);
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// SRU2(DAI1_CRS_PB04_O,DAI0_PB04_I);
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//
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//
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// SRU2(DAI1_PB19_O, SPT0_ACLK_I);
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// SRU2(DAI1_PB19_O, SPT0_BCLK_I);
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// SRU2(DAI1_PB19_O, SPT1_ACLK_I);
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// SRU2(DAI1_PB19_O, SPT1_BCLK_I);
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// SRU2(DAI1_PB19_O, SPT2_ACLK_I);
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// SRU2(DAI1_PB19_O, SPT2_BCLK_I);
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// SRU2(DAI1_PB19_O, SPT3_ACLK_I);
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// SRU2(DAI1_PB19_O, SPT3_BCLK_I);
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//
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// SRU(DAI0_PB04_O, SPT4_ACLK_I);
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// SRU(DAI0_PB04_O, SPT4_BCLK_I);
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//
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// SRU2(DAI1_PB20_O, SPT0_AFS_I);
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// SRU2(DAI1_PB20_O, SPT0_BFS_I);
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// SRU2(DAI1_PB20_O, SPT1_AFS_I);
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// SRU2(DAI1_PB20_O, SPT1_BFS_I);
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// SRU2(DAI1_PB20_O, SPT2_AFS_I);
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// SRU2(DAI1_PB20_O, SPT2_BFS_I);
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// SRU2(DAI1_PB20_O, SPT3_AFS_I);
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// SRU2(DAI1_PB20_O, SPT3_BFS_I);
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//
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// SRU(DAI0_PB03_O, SPT4_AFS_I);
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// SRU(DAI0_PB03_O, SPT4_BFS_I);
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// SRU2(DAI1_PB01_O, SPT0_AD0_I);
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// SRU2(DAI1_PB02_O, SPT0_AD1_I);
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// SRU2(DAI1_PB03_O, SPT0_BD0_I);
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// SRU2(DAI1_PB04_O, SPT0_BD1_I);
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// SRU(DAI0_PB12_O, SPT1_AD0_I);
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// //DSP TDM IN
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// SRU(DAI0_PB05_O, SPT1_AD1_I);
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// //DANTE TDM IN0
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// SRU(DAI0_PB06_O, SPT1_BD0_I);
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// //DANTE TDM IN1
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// //output
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// SRU(HIGH, DAI1_PBEN08_I);
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// //OUT0
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// SRU(SPT2_AD0_O, DAI1_PB08_I);
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// SRU(HIGH, DAI1_PBEN07_I);
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// //OUT1
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// SRU(SPT2_AD1_O, DAI1_PB07_I);
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// SRU(HIGH, DAI1_PBEN06_I);
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// //OUT2
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// SRU(SPT2_BD0_O, DAI1_PB06_I);
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// SRU(HIGH, DAI1_PBEN05_I);
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// //OUT3
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// SRU(SPT2_BD1_O, DAI1_PB05_I);
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// SRU(HIGH, DAI0_PBEN07_I);
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// //DSP TDM OUT
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// SRU(SPT3_AD0_O, DAI0_PB07_I);
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// SRU(HIGH, DAI0_PBEN10_I);
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// //DANTE TDM OUT0
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// SRU(SPT3_AD1_O, DAI0_PB10_I);
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// SRU(HIGH, DAI0_PBEN11_I);
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// //DANTE TDM OUT1
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// SRU(SPT3_BD0_O, DAI0_PB11_I);
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//
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// //DAI1_PB12_I//DAI0_PB08_I
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// SRU2(DAI1_PB12_O, PCG0_EXTCLKC_I);
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// SRU2(HIGH, DAI1_PBEN19_I);
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// SRU2(PCG0_CLKC_O, DAI1_PB19_I);
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// SRU2(HIGH, DAI1_PBEN20_I);
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// SRU2(PCG0_FSC_O, DAI1_PB20_I);
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//
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// {
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// int n ;
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// *pREG_PCG0_CTLC0 =0 ; *pREG_PCG0_CTLC1 =0;
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// for (n=0; n<16; n++)asm("NOP;");
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//
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// *pREG_PCG0_CTLC0 = 512 | (1<<30) | (1<<31) ;;
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// *pREG_PCG0_CTLC1 = 8| (1<<30) | (1<<31) | ((8/2)<<20);
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// }
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// SRU(LOW,DAI0_PBEN03_I); //SCLK
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// SRU(LOW,DAI0_PBEN04_I); //FSCLK
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//
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// SRU(DAI0_PB03_O,SPT0_ACLK_I);
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// SRU(DAI0_PB03_O,SPT0_BCLK_I);
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// SRU(DAI0_PB03_O,SPT1_ACLK_I);
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// SRU(DAI0_PB03_O,SPT1_BCLK_I);
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// SRU(DAI0_PB03_O,SPT2_ACLK_I);
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// SRU(DAI0_PB03_O,SPT2_BCLK_I);
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// SRU(DAI0_PB03_O,SPT3_ACLK_I);
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// SRU(DAI0_PB03_O,SPT3_BCLK_I);
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//
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// SRU(DAI0_PB04_O,SPT0_AFS_I);
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// SRU(DAI0_PB04_O,SPT0_BFS_I);
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// SRU(DAI0_PB04_O,SPT1_AFS_I);
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// SRU(DAI0_PB04_O,SPT1_BFS_I);
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// SRU(DAI0_PB04_O,SPT2_AFS_I);
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// SRU(DAI0_PB04_O,SPT2_BFS_I);
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// SRU(DAI0_PB04_O,SPT3_AFS_I);
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// SRU(DAI0_PB04_O,SPT3_BFS_I);
|
//
|
//
|
// /*
|
// * sp0_ad0 1-16
|
// * sp0_ad1 17-32
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// * sp0_bd0 33-48
|
// * sp0_bd1 48-64
|
// * sp1_ad0 65-80
|
// * sp1_ad1 80-96
|
// */
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//
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// //input..
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// SRU(LOW,DAI0_PBEN01_I); //IN0
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// SRU(DAI0_PB01_O,SPT0_AD0_I);
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// SRU(LOW,DAI0_PBEN02_I); //IN1
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// SRU(DAI0_PB02_O,SPT0_AD1_I);
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// SRU(LOW,DAI0_PBEN05_I); //IN2
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// SRU(DAI0_PB05_O,SPT0_BD0_I);
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// SRU(LOW,DAI0_PBEN06_I); //IN3
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// SRU(DAI0_PB06_O,SPT0_BD1_I);
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// SRU(LOW,DAI0_PBEN07_I); //IN4
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// SRU(DAI0_PB07_O,SPT1_AD0_I);
|
// SRU(LOW,DAI0_PBEN08_I); //IN5
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// SRU(DAI0_PB08_O,SPT1_AD1_I);
|
//
|
// //output
|
// SRU(HIGH,DAI0_PBEN09_I); //OUT0
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// SRU(SPT2_AD0_O,DAI0_PB09_I);
|
// SRU(HIGH,DAI0_PBEN10_I); //OUT1
|
// SRU(SPT2_AD1_O,DAI0_PB10_I);
|
// SRU(HIGH,DAI0_PBEN11_I); //OUT2
|
// SRU(SPT2_BD0_O,DAI0_PB11_I);
|
// SRU(HIGH,DAI0_PBEN12_I); //OUT3
|
// SRU(SPT2_BD1_O,DAI0_PB12_I);
|
// SRU(HIGH,DAI0_PBEN19_I); //OUT4
|
// SRU(SPT3_AD0_O,DAI0_PB19_I);
|
// SRU(HIGH,DAI0_PBEN20_I); //OUT5
|
// SRU(SPT3_AD1_O,DAI0_PB20_I);
|
//
|
// SRU2(DAI1_PB20_O,PCG0_SYNC_CLKA_I);
|
#if 0
|
s8 buffer[1024];
|
u32 i;
|
struct DSPConfig * configs = (struct DSPConfig *)buffer;
|
|
memset(buffer, 0 , 1024);
|
configs->mDspIndex = 0;
|
configs->mDualDsp = 0;
|
configs->mRxNum = 4;
|
configs->mTxNum = 4;
|
|
for(i = 0 ;i < 6 ;i ++) {
|
configs->sports[i].clke = utrue;
|
configs->sports[i].enable = utrue;
|
configs->sports[i].enable_sec = ufalse;
|
configs->sports[i].lfs = utrue;
|
configs->sports[i].mfd = 1;
|
configs->sports[i].opmode = 1 ;
|
configs->sports[i].slots = 2;
|
configs->sports[i].spid = i;
|
configs->sports[i].vld = 2;
|
}
|
|
configs->sports[0].interrupt = utrue;
|
configs->sports[0].rx = utrue;
|
configs->sports[1].rx = utrue;
|
configs->sports[2].rx = utrue;
|
configs->sports[3].rx = utrue;
|
|
|
#define AddRoute(s, d) \
|
configs->routes[configs->mRouteNum].source = s; \
|
configs->routes[configs->mRouteNum].dest = d; \
|
configs->mRouteNum++
|
|
AddRoute(DAI0_PB06_O,SPT0_ACLK_I);
|
AddRoute(DAI0_PB06_O,SPT0_BCLK_I);
|
AddRoute(DAI0_PB06_O,SPT1_ACLK_I);
|
AddRoute(DAI0_PB06_O,SPT1_BCLK_I);
|
AddRoute(DAI0_PB06_O,SPT2_ACLK_I);
|
AddRoute(DAI0_PB06_O,SPT2_BCLK_I);
|
|
AddRoute(DAI0_PB07_O,SPT0_AFS_I);
|
AddRoute(DAI0_PB07_O,SPT0_BFS_I);
|
AddRoute(DAI0_PB07_O,SPT1_AFS_I);
|
AddRoute(DAI0_PB07_O,SPT1_BFS_I);
|
AddRoute(DAI0_PB07_O,SPT2_AFS_I);
|
AddRoute(DAI0_PB07_O,SPT2_BFS_I);
|
|
AddRoute(DAI0_PB08_O,SPT0_AD0_I);
|
AddRoute(DAI0_PB09_O,SPT0_BD0_I);
|
AddRoute(DAI0_PB10_O,SPT1_AD0_I);
|
AddRoute(DAI0_PB11_O,SPT1_BD0_I);
|
|
AddRoute(LOGIC_HIGH,DAI0_PBEN04_I);
|
AddRoute(SPT2_AD0_O,DAI0_PB04_I);
|
AddRoute(LOGIC_HIGH,DAI0_PBEN03_I);
|
AddRoute(SPT2_BD0_O,DAI0_PB03_I);
|
|
|
RouteConfig(configs->routes,configs->mRouteNum);
|
|
SportsConfig(configs->sports);
|
#endif
|
}
|
