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/*
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**
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** Source file generated on August 28, 2018 at 13:37:05.
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**
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** Copyright (C) 2018 Analog Devices Inc., All Rights Reserved.
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**
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** This file is generated automatically based upon the options selected in
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** the Basic Configuration of CGU Initialization configuration dialog. Changes to this configuration should be made by
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** changing the appropriate options rather than editing this file.
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**
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*/
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/** @addtogroup Init_Preload_2156x Processor Initialization Code
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* @{
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*
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*/
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/*!
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* @file adi_pwr_2156x_config.c
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*
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* @brief power Service configuration file
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*
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* @details
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* power Service configuration file
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*/
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#include <sys/platform.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <services/pwr/adi_pwr.h>
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/**********************************************************************************************
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* CGU Configuration Number 0
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**********************************************************************************************/
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/*
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Configuration Number : 0
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SDRAM Mode : DDR3
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SYS_CLKIN0 (MHz) : 25
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Use CGU1 ? : Yes
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//CDU Initialization Options
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SPI(0-2) CLOCK SOURCE (CLKO0) : SCLK0_0 : 125 MHz
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DDR CLOCK (CLKO1) : DCLK0_1 : 533 MHz
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//CGU0 Initialization Options
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fPLL (Desired) : 2000 MHz
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fPLL (Actual) : 2000.0 MHz
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CCLK : 1000.0 MHz
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SYSCLK : 500.0 MHz
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SCLK0 : 125.0 MHz
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SCLK1(SPDIF RX) : 250.0 MHz
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DCLK : 666.667 MHz
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OCLK (LP CLOCK) : 125.0 MHz
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MSEL : 80
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Use DF? : No
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DF : 0
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CSEL : 2
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CCLK to SYSCLK Ratio : 2:1
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S0SEL : 4
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S1SEL : 2
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DSEL : 3
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OSEL : 16
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Use S1SELEX? : No
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S1SELEX : 0
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//CGU1 Initialization Options
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fPLL (Desired) : 1600 MHz
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fPLL (Actual) : 1600 MHz
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DCLK0_1 : 533 MHz
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MSEL : 64
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Use DF? : No
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DF : 0
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DSEL : 3
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*/
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/**********************************************************************************************
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* CGU Configuration Number 0
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**********************************************************************************************/
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#define CFG0_BIT_CGU0_CLKIN 25000000 /*!< Macro for SYS_CLKIN */
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#define CFG0_BIT_CGU1_CLKIN 25000000 /*!< Macro for SYS_CLKIN */
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/* SPI(0-2) CLOCK SOURCE */
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#define CFG0_BIT_CDU0_CFG0_SEL_VALUE 0 /*!< Macro for CDU CFG0 Selection */
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/* DDR CLOCK */
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#define CFG0_BIT_CDU0_CFG1_SEL_VALUE 2 /*!< Macro for CDU CFG1 Selection */
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/**********************************************************************************************
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* CGU Configuration Number 0 Register Values
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**********************************************************************************************/
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/*****************************************CGU0_CTL**********************************************/
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#define CFG0_BIT_CGU0_CTL_DF 0 /*!< Macro for CGU0 DF bit */
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#define CFG0_BIT_CGU0_CTL_MSEL 80 /*!< Macro for CGU0 MSEL field */
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/*****************************************CGU0_DIV**********************************************/
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#define CFG0_BIT_CGU0_DIV_CSEL 2 /*!< Macro for CGU0 CSEL field */
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#define CFG0_BIT_CGU0_DIV_SYSSEL 4 /*!< Macro for CGU0 SYSSEL field */
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#define CFG0_BIT_CGU0_DIV_S0SEL 4 /*!< Macro for CGU0 S0SEL field */
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#define CFG0_BIT_CGU0_DIV_S1SEL 2 /*!< Macro for CGU0 S1SEL field */
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#define CFG0_BIT_CGU0_DIV_DSEL 3 /*!< Macro for CGU0 DSEL field */
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#define CFG0_BIT_CGU0_DIV_OSEL 16 /*!< Macro for CGU0 OSEL field */
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/*****************************************CGU0_DIVEX**********************************************/
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#define CFG0_BIT_CGU0_DIV_S1SELEX 6 //0 /*!< Macro for CGU0 S1SELEX field */
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/*****************************************CGU1_CTL**********************************************/
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#define CFG0_BIT_CGU1_CTL_DF 0 /*!< Macro for CGU1 DF bit */
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#define CFG0_BIT_CGU1_CTL_MSEL 64 /*!< Macro for CGU1 MSEL field */
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/*****************************************CGU1_DIV**********************************************/
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#define CFG0_BIT_CGU1_DIV_DSEL 3 /*!< Macro for CGU1 DSEL field */
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/***********************************************************************************************/
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/**
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* @brief Initializes clocks, including CGU and CDU modules.
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*
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* @return Status
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* - 0: Successful in all the initializations.
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* - 1: Error.
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*/
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uint32_t adi_pwr_cfg0_init(void)
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{
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/* Structure pointer for CGU0 and CGU1 parameters*/
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ADI_PWR_CGU_PARAM_LIST pADI_CGU_Param_List;
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/* Structure pointer for CDU parameters*/
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ADI_PWR_CDU_PARAM_LIST pADI_CDU_Param_List;
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/* CDU Configuration*/
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pADI_CDU_Param_List.cdu_settings[0].cfg_SEL = (ADI_PWR_CDU_CLKIN)CFG0_BIT_CDU0_CFG0_SEL_VALUE;
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pADI_CDU_Param_List.cdu_settings[0].cfg_EN = true;
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pADI_CDU_Param_List.cdu_settings[1].cfg_SEL = (ADI_PWR_CDU_CLKIN)CFG0_BIT_CDU0_CFG1_SEL_VALUE;
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pADI_CDU_Param_List.cdu_settings[1].cfg_EN = true;
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/* CGU0 Configuration*/
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pADI_CGU_Param_List.cgu0_settings.clocksettings.ctl_MSEL = (uint32_t)CFG0_BIT_CGU0_CTL_MSEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.ctl_DF = (uint32_t)CFG0_BIT_CGU0_CTL_DF;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_CSEL = (uint32_t)CFG0_BIT_CGU0_DIV_CSEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_SYSSEL = (uint32_t)CFG0_BIT_CGU0_DIV_SYSSEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_S0SEL = (uint32_t)CFG0_BIT_CGU0_DIV_S0SEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_S1SEL = (uint32_t)CFG0_BIT_CGU0_DIV_S1SEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.divex_S1SELEX = (uint32_t)CFG0_BIT_CGU0_DIV_S1SELEX;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_DSEL = (uint32_t)CFG0_BIT_CGU0_DIV_DSEL;
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pADI_CGU_Param_List.cgu0_settings.clocksettings.div_OSEL = (uint32_t)CFG0_BIT_CGU0_DIV_OSEL;
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pADI_CGU_Param_List.cgu0_settings.clkin = (uint32_t)CFG0_BIT_CGU0_CLKIN;
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pADI_CGU_Param_List.cgu0_settings.enable_IDLE = false;
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pADI_CGU_Param_List.cgu0_settings.enable_SCLK1ExDiv = false;
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/* CGU1 Configuration*/
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pADI_CGU_Param_List.cgu1_settings.clocksettings.ctl_MSEL = (uint32_t)CFG0_BIT_CGU1_CTL_MSEL;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.ctl_DF = (uint32_t)CFG0_BIT_CGU1_CTL_DF;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_CSEL = (uint32_t)0;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_SYSSEL = (uint32_t)0;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_S0SEL = (uint32_t)0;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_S1SEL = (uint32_t)0;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_DSEL = (uint32_t)CFG0_BIT_CGU1_DIV_DSEL;
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pADI_CGU_Param_List.cgu1_settings.clocksettings.div_OSEL = (uint32_t)0;
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pADI_CGU_Param_List.cgu1_settings.clkin = (uint32_t)CFG0_BIT_CGU1_CLKIN;
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pADI_CGU_Param_List.cgu1_settings.enable_IDLE = false;
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/* Set DDR DLL Reset*/
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int delay=9000;
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adi_dmc_lane_reset(true);
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while(delay--);
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/* DDR Self Refresh*/
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#if DDR_SELF_REFRESH
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adi_pwr_ddr_Self_Refresh(0, true);
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adi_pwr_ddr_Self_Refresh(1, true);
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#endif
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/* Initialize all the clocks*/
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if(adi_pwr_ClockInit(&pADI_CGU_Param_List, &pADI_CDU_Param_List) != ADI_PWR_SUCCESS)
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{
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/* Return non-zero */
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return 1u;
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}
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/* Clear DDR DLL Reset*/
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adi_dmc_lane_reset(false);
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delay=9000;
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while(delay--);
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/* DDR Self Refresh*/
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#if DDR_SELF_REFRESH
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adi_pwr_ddr_Self_Refresh(0, false);
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adi_pwr_ddr_Self_Refresh(1, false);
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#endif
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/*Return zero as there are no errors*/
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return 0u;
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}
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/*@}*/
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