#ifndef _DMCINIT_HH__
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#define _DMCINIT_HH__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*****************************************DMC_CTL**********************************************/
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/* ! enable DDR3 controller */
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#define CFG0_BIT_DMC_CTL_DDR3EN 1ul
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_CTL_RDTOWR 5ul
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#define CFG0_REG_DMC_CTL_VALUE ((CFG0_BIT_DMC_CTL_DDR3EN<<BITP_DMC_CTL_DDR3EN)|(BITM_DMC_CTL_INIT)|(CFG0_BIT_DMC_CTL_RDTOWR<<BITP_DMC_CTL_RDTOWR))
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/***************************************** DMC CFG**********************************************/
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_CFG_IFWID (ENUM_DMC_CFG_IFWID16)
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_CFG_SDRWID (ENUM_DMC_CFG_SDRWID16)
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/*! DDR3 memory size*/
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#define CFG0_BIT_DMC_CFG_SDRSIZE (ENUM_DMC_CFG_SDRSIZE8G)
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_CFG_EXTBANK 0ul
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#define CFG0_REG_DMC_CFG_VALUE ((CFG0_BIT_DMC_CFG_IFWID)|(CFG0_BIT_DMC_CFG_SDRWID)|(CFG0_BIT_DMC_CFG_SDRSIZE)|(CFG0_BIT_DMC_CFG_EXTBANK <<BITP_DMC_CFG_EXTBANK))
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/*****************************************DMC_TR0**********************************************/
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/*! Trcd value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TRCD 7ul
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/*! Twtr value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TWTR 5ul
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/*! Trp value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TRP 7ul
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/*! Tras value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TRAS 20ul
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/*! Trc value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TRC 27ul
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/*! Tmrd value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR0_TMRD 4ul
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#define CFG0_REG_DMC_TR0_VALUE ((CFG0_BIT_DMC_TR0_TRCD<<BITP_DMC_TR0_TRCD)|(CFG0_BIT_DMC_TR0_TWTR<<BITP_DMC_TR0_TWTR)|(CFG0_BIT_DMC_TR0_TRP<<BITP_DMC_TR0_TRP)|(CFG0_BIT_DMC_TR0_TRAS<<BITP_DMC_TR0_TRAS)|(CFG0_BIT_DMC_TR0_TRC<<BITP_DMC_TR0_TRC)|(CFG0_BIT_DMC_TR0_TMRD<<BITP_DMC_TR0_TMRD))
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/*****************************************DMC_TR1**********************************************/
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/*! Tref value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR1_TREF 4160ul
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/*! Trfc value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR1_TRFC 187ul
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/*! Trrd value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR1_TRRD 6ul
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#define CFG0_REG_DMC_TR1_VALUE ((CFG0_BIT_DMC_TR1_TREF<<BITP_DMC_TR1_TREF)|(CFG0_BIT_DMC_TR1_TRFC<<BITP_DMC_TR1_TRFC)|(CFG0_BIT_DMC_TR1_TRRD<<BITP_DMC_TR1_TRRD))
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/*****************************************DMC_TR2**********************************************/
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/*! Tfaw value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR2_TFAW 27ul
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/*! Trtp value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR2_TRTP 5ul
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/*! Twr value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR2_TWR 8ul
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/*! Txp value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR2_TXP 4ul
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/*! Tcke value in DDR clock cycles*/
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#define CFG0_BIT_DMC_TR2_TCKE 3ul
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#define CFG0_REG_DMC_TR2_VALUE ((CFG0_BIT_DMC_TR2_TFAW<<BITP_DMC_TR2_TFAW)|(CFG0_BIT_DMC_TR2_TRTP<<BITP_DMC_TR2_TRTP)|(CFG0_BIT_DMC_TR2_TWR<<BITP_DMC_TR2_TWR)|(CFG0_BIT_DMC_TR2_TXP<<BITP_DMC_TR2_TXP)|(CFG0_BIT_DMC_TR2_TCKE<<BITP_DMC_TR2_TCKE))
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/****************************************DMC DLLCTLCFG**********************************************/
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#define ADI_DMC_PARAM_DLLCOUNT 247ul
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/*! ceil ( 15ns/DDRclock in Hz) */
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#define CFG0_REG_DMC_DATACYC 8ul
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#define CFG0_REG_DDR_DLLCTLCFG ((((CFG0_REG_DMC_DATACYC << BITP_DMC_DLLCTL_DATACYC) | (ADI_DMC_PARAM_DLLCOUNT<<BITP_DMC_DLLCTL_DLLCALRDCNT))<<16)|(CFG0_BIT_DMC_CFG_IFWID) |CFG0_BIT_DMC_CFG_SDRWID | CFG0_BIT_DMC_CFG_SDRSIZE)
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/****************************************DMC MR0**********************************************/
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_MR0_BLEN 0ul
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/*! CAS Read latency bit 0 value*/
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#define CFG0_BIT_DMC_MR0_CL0 0ul
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/*! CAS Read latency [2:1] bits*/
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#define CFG0_BIT_DMC_MR0_CL 3ul
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_MR0_DLLRST 1ul
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/*! Write recovery value*/
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#define CFG0_BIT_DMC_MR0_WRRECOV 4ul
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#define CFG0_REG_DMC_MR0_VALUE ((CFG0_BIT_DMC_MR0_BLEN<<BITP_DMC_MR_BLEN)|(CFG0_BIT_DMC_MR0_CL0<<BITP_DMC_MR_CL0)|(CFG0_BIT_DMC_MR0_CL<<BITP_DMC_MR_CL)|(CFG0_BIT_DMC_MR0_DLLRST<<BITP_DMC_MR_DLLRST)|(CFG0_BIT_DMC_MR0_WRRECOV<<BITP_DMC_MR_WRRECOV))
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/****************************************DMC MR1**********************************************/
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/*! Constant value, should not be altered*/
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#define CFG0_BIT_DMC_MR1_DLLEN 0ul
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/*! Bit 0 of the output DS*/
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#define CFG0_BIT_DMC_MR1_DIC0 0ul
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/*! Bit 0 of the ODT*/
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#define CFG0_BIT_DMC_MR1_RTT0 1ul
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/*! Additive latency setting*/
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#define CFG0_BIT_DMC_MR1_AL 1ul
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/*! Bit 1 of the output DS*/
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#define CFG0_BIT_DMC_MR1_DIC1 0ul
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/*! Bit 1 of the ODT*/
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#define CFG0_BIT_DMC_MR1_RTT1 0ul
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/*! Bit 2 of the ODT*/
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#define CFG0_BIT_DMC_MR1_RTT2 0ul
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#define CFG0_BIT_DMC_MR1_TDQS 0ul
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#define CFG0_BIT_DMC_MR1_QOFF 0ul
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#define CFG0_REG_DMC_MR1_VALUE ((CFG0_BIT_DMC_MR1_DLLEN<<BITP_DMC_MR1_DLLEN)|(CFG0_BIT_DMC_MR1_DIC0<<BITP_DMC_MR1_DIC0)|(CFG0_BIT_DMC_MR1_RTT0<<BITP_DMC_MR1_RTT0)|(CFG0_BIT_DMC_MR1_AL<<BITP_DMC_MR1_AL)|(CFG0_BIT_DMC_MR1_DIC1<<BITP_DMC_MR1_DIC1)|(CFG0_BIT_DMC_MR1_RTT1<<BITP_DMC_MR1_RTT1)|(CFG0_BIT_DMC_MR1_RTT2<<BITP_DMC_MR1_RTT2)|(CFG0_BIT_DMC_MR1_TDQS<<BITP_DMC_MR1_TDQS)|(CFG0_BIT_DMC_MR1_QOFF<<BITP_DMC_MR1_QOFF))
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/**************************************** DMC MR2MR3**********************************************/
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/*! CAS write latency*/
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#define CFG0_BIT_DMC_MR2_CWL 1ul
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#define CFG0_REG_DMC_MR2MR3 (((CFG0_BIT_DMC_MR2_CWL<<BITP_DMC_MR2_CWL))<<16)
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#define CFG0_REG_DMC_MRMR1 (CFG0_REG_DMC_MR1_VALUE|(CFG0_REG_DMC_MR0_VALUE<<16ul))
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/*! Core clock and DCLK ratio*/
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#define csel_dsel_r 10ul
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#define TrigCalib 0ul
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#define DelayTrim 0ul
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#define DqsTrim 0ul
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#define ClkTrim 0ul
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#define CLKDIR 0ul
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#define Bypasscode 0ul
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#define Dqscode 0ul
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#define Clkcode 0ul
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#define OfstdCycle 2ul
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/* including missing declarations*/
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#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Reset the Lane DLL */
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#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Reset the Lane DLL */
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#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Compute Datacycle */
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#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Compute Datacycle */
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#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT (_ADI_MSK_3(0x08000000,0x08000000UL, uint32_t )) /* Reset the Data Pads */
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#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT (_ADI_MSK_3(0x08000000,0x08000000UL, uint32_t )) /* Reset the Data Pads */
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#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */
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#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */
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typedef enum
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{
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ADI_DMC_SUCCESS=0u,
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ADI_DMC_FAILURE
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}ADI_DMC_RESULT;
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/* structure which holds DMC register values */
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typedef struct
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{
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uint32_t ulDDR_DLLCTLCFG; /*!< Content of DDR DLLCTL and DMC_CFG register */
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uint32_t ulDDR_EMR2EMR3; /*!< Content of the DDR EMR2 and EMR3 Register */
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uint32_t ulDDR_CTL; /*!< Content of the DDR Control */
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uint32_t ulDDR_MREMR1; /*!< Content of the DDR MR and EMR1 Register */
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uint32_t ulDDR_TR0; /*!< Content of the DDR Timing Register */
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uint32_t ulDDR_TR1; /*!< Content of the DDR Timing Register */
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uint32_t ulDDR_TR2; /*!< Content of the DDR Timing Register */
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uint32_t ulDDR_ZQCTL0; /*!< Content of ZQCTL0 register */
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uint32_t ulDDR_ZQCTL1; /*!< Content of ZQCTL1 register */
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uint32_t ulDDR_ZQCTL2; /*!< Content of ZQCTL2 register */
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}ADI_DMC_CONFIG;
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int dmc_cfg0_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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