/*
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* dmc.c
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*
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* Created on: 2021Äê10ÔÂ30ÈÕ
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* Author: graydon
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <assert.h>
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#include <sys/platform.h>
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#include <sys/adi_core.h>
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#include "DMCInit.h"
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/* delay function */
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#pragma inline
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static void dmcdelay(uint32_t delay)
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{
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uint32_t i;
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for(i=delay; i>0ul; i--){
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NOP();
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}
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}
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/* DMC phy ZQ calibration routine
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* The first step in DMC initialization
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*/
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void adi_dmc_phy_calibration(ADI_DMC_CONFIG *pConfig,uint32_t csel_dsel)
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{
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/* Program the ODT and drive strength values */
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*pREG_DMC0_DDR_ZQ_CTL0 = pConfig->ulDDR_ZQCTL0;
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*pREG_DMC0_DDR_ZQ_CTL1 = pConfig->ulDDR_ZQCTL1;
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*pREG_DMC0_DDR_ZQ_CTL2 = pConfig->ulDDR_ZQCTL2;
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/* Generate the trigger */
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*pREG_DMC0_DDR_CA_CTL = 0x00000000ul ;
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*pREG_DMC0_DDR_ROOT_CTL = 0x00000000ul;
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*pREG_DMC0_DDR_ROOT_CTL = 0x00010000ul;
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dmcdelay(csel_dsel*8000ul);
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/* The [31:26] bits may change if pad ring changes */
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*pREG_DMC0_DDR_CA_CTL = 0x0C000001ul|TrigCalib;
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dmcdelay(csel_dsel*8000ul);
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*pREG_DMC0_DDR_CA_CTL = 0x00000000ul ;
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*pREG_DMC0_DDR_ROOT_CTL = 0x00000000ul ;
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/* DQS delay trim*/
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if (DelayTrim)
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{
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*pREG_DMC0_DDR_LANE0_CTL1|= (((Bypasscode)<<BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & BITM_DMC_DDR_LANE0_CTL1_BYPCODE)|BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN;
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*pREG_DMC0_DDR_LANE1_CTL1|=(((Bypasscode)<<BITP_DMC_DDR_LANE1_CTL1_BYPCODE) & BITM_DMC_DDR_LANE1_CTL1_BYPCODE)|BITM_DMC_DDR_LANE1_CTL1_BYPDELCHAINEN;
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}
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/* DQS duty trim */
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if(DqsTrim)
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{
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*pREG_DMC0_DDR_LANE0_CTL0|= ((Dqscode)<<BITP_DMC_DDR_LANE0_CTL0_BYPENB) & (BITM_DMC_DDR_LANE1_CTL0_BYPENB|BITM_DMC_DDR_LANE0_CTL0_BYPSELP|BITM_DMC_DDR_LANE0_CTL0_BYPCODE);
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*pREG_DMC0_DDR_LANE1_CTL0|=((Dqscode)<<BITP_DMC_DDR_LANE1_CTL0_BYPENB) & (BITM_DMC_DDR_LANE1_CTL1_BYPCODE|BITM_DMC_DDR_LANE1_CTL0_BYPSELP|BITM_DMC_DDR_LANE1_CTL0_BYPCODE);
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}
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/* Clock duty trim */
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if(ClkTrim)
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{
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*pREG_DMC0_DDR_CA_CTL|=(((Clkcode <<BITP_DMC_DDR_CA_CTL_BYPCODE1)&BITM_DMC_DDR_CA_CTL_BYPCODE1)|BITM_DMC_DDR_CA_CTL_BYPENB|((CLKDIR<<BITP_DMC_DDR_CA_CTL_BYPSELP)&BITM_DMC_DDR_CA_CTL_BYPSELP));
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}
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}
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/* DMC lane reset routine
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* DMC lane reset should be performed when DMC clock is changed
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* Sequence: Before changing the DDR clock frequency reset the lane , call cgu routine to change the DMC clock frequency
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* Then take DMC lanes out of reset
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*/
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void adi_dmc_lane_reset(bool reset)
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{
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if (reset) {
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*pREG_DMC0_DDR_LANE0_CTL0 |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL;
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*pREG_DMC0_DDR_LANE1_CTL0 |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL;
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} else {
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*pREG_DMC0_DDR_LANE0_CTL0 &= ~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL;
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*pREG_DMC0_DDR_LANE1_CTL0 &= ~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL;
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}
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}
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/* dmc_ctrl_init() configures DMC controller
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* It returns ADI_DMC_SUCCESS on success and ADI_DMC_FAILURE on failure
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*/
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ADI_DMC_RESULT adi_dmc_ctrl_init(ADI_DMC_CONFIG *pConfig,uint32_t csel_dsel)
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{
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uint32_t phyphase,rd_cnt,t_EMR1,t_EMR3, t_CTL,data_cyc;
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/* program timing registers*/
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*pREG_DMC0_CFG = (pConfig->ulDDR_DLLCTLCFG) & 0xFFFFul;
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*pREG_DMC0_TR0 = pConfig->ulDDR_TR0;
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*pREG_DMC0_TR1 = pConfig->ulDDR_TR1;
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*pREG_DMC0_TR2 = pConfig->ulDDR_TR2;
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/* program shadow registers */
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*pREG_DMC0_MR = ((pConfig->ulDDR_MREMR1) >> 16ul) & 0xFFFFul;
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*pREG_DMC0_MR1 = (pConfig->ulDDR_MREMR1) & 0xFFFFul;
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*pREG_DMC0_MR2 = (pConfig->ulDDR_EMR2EMR3)>>16ul & 0xFFFFul;
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*pREG_DMC0_EMR3 =(pConfig->ulDDR_EMR2EMR3) & 0xFFFFul;
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/* program Dll timing register */
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*pREG_DMC0_DLLCTL = ((pConfig->ulDDR_DLLCTLCFG) >> 16ul) & 0xFFFFul;
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dmcdelay(csel_dsel*2000ul);
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*pREG_DMC0_DDR_CA_CTL |=BITM_DMC_DDR_CA_CTL_SW_REFRESH;
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dmcdelay(csel_dsel_r*5ul);
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*pREG_DMC0_DDR_ROOT_CTL |= BITM_DMC_DDR_ROOT_CTL_SW_REFRESH | (OfstdCycle << BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE);
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/* Start DMC initialization */
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*pREG_DMC0_CTL = pConfig->ulDDR_CTL;
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dmcdelay(csel_dsel*12500ul);
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/* Add necessary delay depending on the configuration */
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t_EMR1=(pConfig->ulDDR_MREMR1 & BITM_DMC_MR1_WL)>>BITP_DMC_MR1_WL;
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if(t_EMR1)
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{
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dmcdelay(csel_dsel_r*600ul);
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while(((*pREG_DMC0_MR1 & BITM_DMC_MR1_WL)>>BITP_DMC_MR1_WL) != 0ul)
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{
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}
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}
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t_EMR3=(pConfig->ulDDR_EMR2EMR3 & BITM_DMC_EMR3_MPR)>>BITP_DMC_EMR3_MPR;
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if(t_EMR3)
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{
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dmcdelay(csel_dsel*2000ul);
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while(((*pREG_DMC0_EMR3 & BITM_DMC_EMR3_MPR)>>BITP_DMC_EMR3_MPR) != 0ul)
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{
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}
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}
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t_CTL=(pConfig->ulDDR_CTL & BITM_DMC_CTL_RL_DQS)>>BITP_DMC_CTL_RL_DQS;
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if(t_CTL)
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{
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dmcdelay(csel_dsel*600ul);
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while(((*pREG_DMC0_CTL & BITM_DMC_CTL_RL_DQS)>>BITP_DMC_CTL_RL_DQS) != 0ul)
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{
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}
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}
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/* check if DMC initialization finished, if not return error */
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_INITDONE) !=BITM_DMC_STAT_INITDONE);
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/* End of DMC controller configuration, Start of Phy control registers */
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/* toggle DCYCLE */
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*pREG_DMC0_DDR_LANE0_CTL1 |= BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE;
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*pREG_DMC0_DDR_LANE1_CTL1 |= BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE;
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dmcdelay(csel_dsel_r*10ul);
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*pREG_DMC0_DDR_LANE0_CTL1 &= (~BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE);
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*pREG_DMC0_DDR_LANE1_CTL1 &= (~BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE);
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/* toggle RSTDAT */
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*pREG_DMC0_DDR_LANE0_CTL0 |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT;
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*pREG_DMC0_DDR_LANE0_CTL0 &= (~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT);
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*pREG_DMC0_DDR_LANE1_CTL0 |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT;
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*pREG_DMC0_DDR_LANE1_CTL0 &= (~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT);
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dmcdelay(csel_dsel*2500ul);
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/* Program phyphase*/
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phyphase = (*pREG_DMC0_STAT & BITM_DMC_STAT_PHYRDPHASE)>>BITP_DMC_STAT_PHYRDPHASE;
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data_cyc= (phyphase << BITP_DMC_DLLCTL_DATACYC) & BITM_DMC_DLLCTL_DATACYC;
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rd_cnt = ((pConfig->ulDDR_DLLCTLCFG) >> 16);
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rd_cnt <<= BITP_DMC_DLLCTL_DLLCALRDCNT;
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rd_cnt &= BITM_DMC_DLLCTL_DLLCALRDCNT;
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*pREG_DMC0_DLLCTL =rd_cnt|data_cyc;
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*pREG_DMC0_CTL = (pConfig->ulDDR_CTL & (~BITM_DMC_CTL_INIT) & (~BITM_DMC_CTL_RL_DQS));
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return ADI_DMC_SUCCESS;
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}
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/* In order to preserve ddr content while changing DMC clock, put memory in self refresh mode
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*
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* sequence: program DMC controller to enter self refresh mode. No further access should be issued to ddr memory
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* call cgu routines to change DMC clock
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* exit self-refresh mode
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*
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*/
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void adi_dmc_self_refresh(bool enter)
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{
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if (enter){
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/*Set the SRREQ bit to enter self refresh mode*/
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_IDLE)==0ul)
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{
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}
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*pREG_DMC0_CTL|= BITM_DMC_CTL_SRREQ;
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/*Wait for self refresh acknowledge from the controller*/
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_SRACK)==0ul)
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{
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}
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}else{
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/*clear the SRREQ bit to exit self refresh mode*/
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*pREG_DMC0_CTL &= ~BITM_DMC_CTL_SRREQ;
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/*Wait for self refresh acknowledge from the controller*/
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_SRACK)==1ul)
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{
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}
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/*Wait for the DMC to be in IDLE state*/
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_IDLE)==0ul)
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{
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}
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*pREG_DMC0_CTL |=BITM_DMC_CTL_DLLCAL;
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/*Wait for DLL calib*/
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while((*pREG_DMC0_STAT & BITM_DMC_STAT_DLLCALDONE)==0ul)
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{
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}
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}
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}
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/**
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* @brief Initializes DMC controller.
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*
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* @return Status
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* - 0: Successful in initializing DMC controller.
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* - 1: Error.
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*/
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int dmc_cfg0_init(void)
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{
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static ADI_DMC_CONFIG CONFIG533 =
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{
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CFG0_REG_DDR_DLLCTLCFG,
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CFG0_REG_DMC_MR2MR3,
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CFG0_REG_DMC_CTL_VALUE,
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CFG0_REG_DMC_MRMR1,
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CFG0_REG_DMC_TR0_VALUE,
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CFG0_REG_DMC_TR1_VALUE,
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CFG0_REG_DMC_TR2_VALUE,
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0x00782828ul,
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0ul,
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0x70000000ul
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};
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/* Initialize DMC PHY registers*/
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adi_dmc_phy_calibration((&CONFIG533),csel_dsel_r);
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/* Initialize DMC Controller*/
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if(adi_dmc_ctrl_init((&CONFIG533),csel_dsel_r) != ADI_DMC_SUCCESS)
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{
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/* Return non-zero */
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return 1u;
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}
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return 0u;
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}
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