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S 4 ( .strtab .symtab .attributes seg_swco .epctext sru2mask. .LNsru2mask. .LN0 _GROUP. IN_SHIFT. .LN.sru2mask..end .sru2mask..end srumask. .LNsrumask. .LN1 .LN.srumask..end .srumask..end sru2field. .LNsru2field. .LN2 A2_out.0. B2_out.1. C2_out.2. D2_out.3. E2_out.4. F2_out.5. G2_out.6. .LN.sru2field..end .sru2field..end srufield. .LNsrufield. .LN3 A_out.7. B_out.8. C_out.9. D_out.10. E_out.11. F_out.12. G_out.13. .LN.srufield..end .srufield..end dai_route. .LNdai_route. .LN4 .P54L8 .P54L1 .P54L7 .P54L6 .P54L5 .P54L4 .P54L2 .LN5 .LCJ0 .__constant .__operator .LN6 .LN7 .LCJ1 .LN8 _REG. .LN9 .P54L3 .LN10 .LCJ2 .LN11 .LN12 .LCJ3 .LN13 .LN14 .LN.dai_route..end .dai_route..end .epctext.end .debug_abbrev .epcabbrev .epcabbrev.end .debug_info .epcdebug .epcline .epcdebug.end .debug_line .epcline.end .debug_pubnames .epcpubnames .epcpubnames.end .debug_aranges .epcaranges .epcaranges.end seg_dmda ..\drv\sru_dai.c .rela.seg_swco .align.seg_swco .rela..debug_info .rela..debug_line .rela..debug_pubnames .rela..debug_aranges .align.seg_dmda .commandLine .adi.attributes ñÿ $ : 1 ] L o Y v > ] _ ¾ º F h W E c N i R u Y { j Ð É U M × Ï 0 & 5 * @ 1 K B É ¾ Â º 9 H > _ ã E P j ÿ ø ñ õ ê ç Ü Ù ! $ ! ¡ v ± M Ù ¿ Ê à \ h @ å ø ô ï / < u & ¤ v ë ± Ã Õ
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$ I ! 7"/ .2 ' I? I 4 4 2 I ,? & I ð ..\drv\sru_dai.c D:\project\plugscard\dsp21569\DSP-21569\Debug C/C++ Compiler : SHARC version 8.15.0.0 (Apr 20 2022 18:13:48)
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[ce7a0e45923b14815a072ad54a672fd5bfe93d2a]
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Copyright (c) 1997-2022 Analog Devices, Inc.
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Copyright (c) 1998-2014 Edison Design Group, Inc.
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Copyright (c) 1997-1999 Edinburgh Portable Compilers, Ltd.
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bool wchar_t char signed char unsigned char short signed short unsigned short int signed int unsigned int long signed long unsigned long long long signed long long unsigned long long short _Fract áÿÿÿ_Fract áÿÿÿlong _Fract áÿÿÿunsigned short _Fract àÿÿÿunsigned _Fract àÿÿÿunsigned long _Fract àÿÿÿfloat double long double _Complex float _Complex double _Complex long double void * _Ptrdifft _Sizet _Int32t ç _Uint32t ö _Longlong 2 _ULonglong U _Wintt ß _Wchart ß va_list é _Va_list ï ? _Mbstatet _Wchar Û # _State # _Mbstatet _Sysch_t int8_t int16_t ± int32_t uint8_t uint16_t Ì uint32_t int_least8_t int_least16_t ± uint_least8_t uint_least16_t Ì int_least32_t uint_least32_t int_fast8_t int_fast16_t ± uint_fast8_t uint_fast16_t Ì int_fast32_t uint_fast32_t uintptr_t ö intptr_t ß int64_t uint64_t ½ int_least64_t uint_least64_t ½ int_fast64_t uint_fast64_t ½ intmax_t uintmax_t ½ ¬ ADI_CORE_ENABLE_SUCCESS ADI_CORE_ENABLE_INVALID_CORE ADI_CORE_ENABLE_CURRENT_CORE ADI_CORE_ENABLE_STATUS J å ADI_CORE_SHARC0 ADI_CORE_ID É k _adiCacheStatus adi_cache_success adi_cache_unsuitable_rr adi_cache_anom_rr_fail adi_cache_failure adiCacheStatus ÷ _adiRangeReg adi_cache_rr0 adi_cache_rr1 adi_cache_rr2 adi_cache_rr3 adi_cache_rr4 adi_cache_rr5
adi_cache_rr6 adi_cache_rr7 adiRangeReg Ç _adiRangeSetting adi_cache_disable_range adi_cache_noncacheable_range adi_cache_flush_range adi_cache_lock_range adi_cache_wt_range adiRangeSetting 0 õ __builtin_quad acc80 Ý size_t ptrdiff_t ß s8 s16 ± s32 ß u8 u16 Ì u32 ö u64 U ufloat ubool ; udouble
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void uvoid uvoidptr h ¸ ; name_t ª DAI0_PB01_O DAI0_PB02_O DAI0_PB03_O DAI0_PB04_O DAI0_PB05_O DAI0_PB06_O DAI0_PB07_O DAI0_PB08_O DAI0_PB09_O DAI0_PB10_O DAI0_PB11_O
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DAI0_PB12_O DAI0_PB19_O DAI0_PB20_O DAI1_PB01_O DAI1_PB02_O DAI1_PB03_O DAI1_PB04_O DAI1_PB05_O DAI1_PB06_O DAI1_PB07_O DAI1_PB08_O DAI1_PB09_O DAI1_PB10_O DAI1_PB11_O DAI1_PB12_O DAI1_PB19_O DAI1_PB20_O SPT0_AD0_O SPT0_AD1_O SPT0_BD0_O SPT0_BD1_O SPT1_AD0_O SPT1_AD1_O ! SPT1_BD0_O " SPT1_BD1_O # SPT2_AD0_O $ SPT2_AD1_O % SPT2_BD0_O & SPT2_BD1_O ' SPT3_AD0_O ( SPT3_AD1_O ) SPT3_BD0_O * SPT3_BD1_O + SPT4_AD0_O , SPT4_AD1_O - SPT4_BD0_O . SPT4_BD1_O / SPT5_AD0_O 0 SPT5_AD1_O 1 SPT5_BD0_O 2 SPT5_BD1_O 3 SPT6_AD0_O 4 SPT6_AD1_O 5 SPT6_BD0_O 6 SPT6_BD1_O 7 SPT7_AD0_O 8 SPT7_AD1_O 9 SPT7_BD0_O : SPT7_BD1_O ; PCG_CLKA_O < PCG_CLKB_O = PCG_CLKC_O > PCG_CLKD_O ? PCG_FSA_O À PCG_FSB_O Á PCG_FSC_O Â PCG_FSD_O Ã SRC0_DAT_OP_O Ä SRC0_TDM_IP_O Å SRC1_DAT_OP_O Æ SRC1_TDM_IP_O Ç SRC2_DAT_OP_O È SRC2_TDM_IP_O É SRC3_DAT_OP_O Ê SRC3_TDM_IP_O Ë LOGIC_LOW Ì LOGIC_HIGH Í SourceSignalCount Î SourceSignal Å ß DAI0_PB01_I DAI0_PB02_I DAI0_PB03_I DAI0_PB04_I DAI0_PB05_I DAI0_PB06_I DAI0_PB07_I DAI0_PB08_I DAI0_PB09_I DAI0_PB10_I DAI0_PB11_I
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DAI0_PB12_I DAI0_PB19_I DAI0_PB20_I DAI1_PB01_I DAI1_PB02_I DAI1_PB03_I DAI1_PB04_I DAI1_PB05_I DAI1_PB06_I DAI1_PB07_I DAI1_PB08_I DAI1_PB09_I DAI1_PB10_I DAI1_PB11_I DAI1_PB12_I DAI1_PB19_I DAI1_PB20_I DAI0_PBEN01_I DAI0_PBEN02_I DAI0_PBEN03_I DAI0_PBEN04_I DAI0_PBEN05_I DAI0_PBEN06_I ! DAI0_PBEN07_I " DAI0_PBEN08_I # DAI0_PBEN09_I $ DAI0_PBEN10_I % DAI0_PBEN11_I & DAI0_PBEN12_I ' DAI0_PBEN19_I ( DAI0_PBEN20_I ) DAI1_PBEN01_I * DAI1_PBEN02_I + DAI1_PBEN03_I , DAI1_PBEN04_I - DAI1_PBEN05_I . DAI1_PBEN06_I / DAI1_PBEN07_I 0 DAI1_PBEN08_I 1 DAI1_PBEN09_I 2 DAI1_PBEN10_I 3 DAI1_PBEN11_I 4 DAI1_PBEN12_I 5 DAI1_PBEN19_I 6 DAI1_PBEN20_I 7 SPT0_ACLK_I 8 SPT0_BCLK_I 9 SPT0_AFS_I : SPT0_BFS_I ; SPT0_AD0_I < SPT0_AD1_I = SPT0_BD0_I > SPT0_BD1_I ? SPT1_ACLK_I À SPT1_BCLK_I Á SPT1_AFS_I Â SPT1_BFS_I Ã SPT1_AD0_I Ä SPT1_AD1_I Å SPT1_BD0_I Æ SPT1_BD1_I Ç SPT2_ACLK_I È SPT2_BCLK_I É SPT2_AFS_I Ê SPT2_BFS_I Ë SPT2_AD0_I Ì SPT2_AD1_I Í SPT2_BD0_I Î SPT2_BD1_I Ï SPT3_ACLK_I Ð SPT3_BCLK_I Ñ SPT3_AFS_I Ò SPT3_BFS_I Ó SPT3_AD0_I Ô SPT3_AD1_I Õ SPT3_BD0_I Ö SPT3_BD1_I × SPT4_ACLK_I Ø SPT4_BCLK_I Ù SPT4_AFS_I Ú SPT4_BFS_I Û SPT4_AD0_I Ü SPT4_AD1_I Ý SPT4_BD0_I Þ SPT4_BD1_I ß SPT5_ACLK_I à SPT5_BCLK_I á SPT5_AFS_I â SPT5_BFS_I ã SPT5_AD0_I ä SPT5_AD1_I å SPT5_BD0_I æ SPT5_BD1_I ç SPT6_ACLK_I è SPT6_BCLK_I é SPT6_AFS_I ê SPT6_BFS_I ë SPT6_AD0_I ì SPT6_AD1_I í SPT6_BD0_I î SPT6_BD1_I ï SPT7_ACLK_I ð SPT7_BCLK_I ñ SPT7_AFS_I ò SPT7_BFS_I ó SPT7_AD0_I ô SPT7_AD1_I õ SPT7_BD0_I ö SPT7_BD1_I ÷ PCG_EXTA_I ø PCG_EXTB_I ù PCG_EXTC_I ú PCG_EXTD_I û SRC0_CLK_IP_I ü SRC0_FS_IP_I ý SRC0_DAT_IP_I þ SRC0_CLK_OP_I ÿ SRC0_FS_OP_I SRC0_TDM_OP_I SRC1_CLK_IP_I SRC1_FS_IP_I SRC1_DAT_IP_I SRC1_CLK_OP_I
SRC1_FS_OP_I SRC1_TDM_OP_I SRC2_CLK_IP_I SRC2_FS_IP_I SRC2_DAT_IP_I SRC2_CLK_OP_I SRC2_FS_OP_I SRC2_TDM_OP_I SRC3_CLK_IP_I SRC3_FS_IP_I SRC3_DAT_IP_I SRC3_CLK_OP_I SRC3_FS_OP_I SRC3_TDM_OP_I DestSignalCount DestSignal * ; sru2mask N source t dest ß x
srumask N source t dest ß x y sru2field N source t dest ß x A2_out Ò B2_out Ä C2_out ¶ D2_out ¨ E2_out F2_out G2_out ~ N y N M y N M ¨ y N M ¶ y N M Ä y N M Ò y N M à y N M Ì srufield N source t dest ß x A_out B_out C_out D_out ö E_out è F_out Ú G_out Ì Ú y N M è y N M ö y N M y N M y N M y N M . y N M z dai_route o source t dest ß x _REG â _GROUP Ò IN_SHIFT Â Ò N â N ò N ö
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..\drv\ D:\project\plugscard\dsp21569\DSP-21569\system D:\project\plugscard\dsp21569\DSP-21569\lib\zlib D:\project\plugscard\dsp21569\DSP-21569\inc C:\Analog Devices\CrossCore Embedded Studio 2.11.0\SHARC\include C:\Analog Devices\CrossCore Embedded Studio 2.11.0\SHARC\include\sys\ ..\drv\sru_dai.c ªßâsru.h Ô¦ sru21569.h ì¿êäsys\platform.h è¿þ platform_include.h Ô¦µ>cdef21569.h Ü¿ sys\ADSP-2156x-core_cdef.h è¿×istdint.h ì¿ÿMyvals.h ä¿Ç¤ADSP-2156x-core.h è¿·
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def21569.h Ü¿Î.sys\ADSP_2156x_HPC.h æ¿ë
sys\ADSP_SC5xx_legacy.h ä¿ôßsys\def2156x_id_macros.h ä¿À9sys\ADSP_2156x_HPC_cdef.h ä¿Ä sys\internal_system_prototypes.h è¿û processor_include.h 쿱21569.h Ü¿!sys\adi_core.h 俵"sys\cache.h è¿*stdbool.h Ü¿builtins.h Ò»Äøsys\builtins_support.h è¿Ú
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sru_dai.h ª¤ typedefs.h ìºÅ
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û
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Ú É Ù
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q ô ð sru2mask ; srumask
sru2field à srufield . dai_route z _REG _GROUP ¨ IN_SHIFT < 1 1 1 1 1 1 1 1 1 1 1 1 1 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1¡ 1à 1à 1à 1à 1à 1ä 1ä 1ä 1ä 1ä 1è 1è 1ì 1ì 1à¡ 1à¡ 1à¡ 1à¡ 1à¡ 1ä¡ 1ä¡ 1ä¡ 1ä¡ 1ä¡ 1è¡ 1è¡ 1ì¡ 1ì¡ 1À 1À 1@ 1@ 1 1 1 1 1À 1À 1@ 1@ 1 1 1 1 1À 1À 1@ 1@ 1 1 1 1 1Ô 1Ô 1P 1P 1 1 1 1 1À 1À 1@¡ 1@¡ 1 ¡ 1 ¡ 1 ¡ 1 ¡ 1À 1À 1@¡ 1@¡ 1 ¡ 1¡ 1¡ 1¡ 1À 1À 1@¡ 1@¡ 1¡ 1¡ 1¡ 1¡ 1Ô 1Ô 1P¡ 1P¡ 1¡ 1¡ 1¡ 1¡ 1Ð 1Ð 1Ð 1Ð 1Ä 1D 1 1Ä 1D 1 1Ä 1D 1 1Ä 1D 1 1Ä 1D 1 1Ä 1D 1 1È 1H 1 1È 1H 1 1
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