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DG 4 ( .strtab .symtab .attributes seg_swco .epctext sport_enable. .LNsport_enable. .LN0 .LN1 .LN.sport_enable..end .sport_enable..end get_sport_regs. .LNget_sport_regs. .LN2 .P39L2 .LN3 gSports. .P39L4 .LN4 .LN5 .LN.get_sport_regs..end .get_sport_regs..end sport_config. .LNsport_config. .LN6 .LN7 get_dma_regs. .LCJ0 .__constant .__operator .LN8 .LN9 sp_desc. .LN10 .LN11 SAMPLE_NUM. .LN12 .P41L2 .LN13 .LN14 .P41L3 .LN15 .LN16 sram_malloc. .LCJ1 .LN17 .LN18 .P41L5 .LN19 .sdmaBuf.0 _printf32. .LCJ2 .LN20 .P41L6 .LN21 .LN22 mCodecNum. mAudioCodec. .LN23 .LN24 .LN25 .LN26 .LN27 .LN28 .LN29 .LN30 .LN31 .LN32 .LN33 .LN34 dma_config. .LCJ3 .LN35 .LN36 .LN37 .P41L8 .LN38 .LN39 .P41L9 .LN40 .LN41 .P41L11 .LN42 .LN43 .P41L13 .P41L15 .LN44 .LN45 .LN46 .LN47 .P41L12 .LN48 .LN.sport_config..end .sport_config..end .epctext.end seg_dmda .epcbss .epcbss.end .debug_abbrev .epcabbrev .epcabbrev.end .debug_info .epcdebug .epcline .epcdebug.end .debug_line .epcline.end .debug_pubnames .epcpubnames .epcpubnames.end .debug_aranges .epcaranges .epcaranges.end ..\drv\sport.c .rela.seg_swco .align.seg_swco .align.seg_dmda .rela..debug_info .rela..debug_line .rela..debug_pubnames .rela..debug_aranges .commandLine .adi.attributes ñÿ3 N µ ê § u K Ï : ý Õ X N S d ^ j m | u { ¢ » Á Î ¤ ! ð ª ý ¸ ! Ä ' Ñ - à 3 ï 9 þ ? E ° & K Q $ W * ] 1 c @ { N U o w { Å 0 § ~ » Á × ¢ Ý « ã ³ é Ê ÷ Í Ê 2 E G Q N V P
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I ! 7"/ 2 ' 2 ' I I $ 2 < 5 I & I .2 ' ? I 4 .2 ' I? 4 2 I ,? ¥! ..\drv\sport.c D:\project\plugscard\dsp21569\DSP-21569\Debug C/C++ Compiler : SHARC version 8.15.0.0 (Apr 20 2022 18:13:48)
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[ce7a0e45923b14815a072ad54a672fd5bfe93d2a]
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Copyright (c) 1997-2022 Analog Devices, Inc.
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Copyright (c) 1998-2014 Edison Design Group, Inc.
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Copyright (c) 1997-1999 Edinburgh Portable Compilers, Ltd.
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bool wchar_t char signed char unsigned char short signed short unsigned short int signed int unsigned int long signed long unsigned long long long signed long long unsigned long long short _Fract áÿÿÿ_Fract áÿÿÿlong _Fract áÿÿÿunsigned short _Fract àÿÿÿunsigned _Fract àÿÿÿunsigned long _Fract àÿÿÿfloat double long double _Complex float _Complex double _Complex long double void * _Ptrdifft _Sizet _Int32t å _Uint32t ô _Longlong 0 _ULonglong S _Wintt Ý _Wchart Ý va_list ç _Va_list í = _Mbstatet _Wchar Ù # _State # _Mbstatet
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_Sysch_t int8_t int16_t ¯ int32_t uint8_t uint16_t Ê uint32_t int_least8_t int_least16_t ¯ uint_least8_t uint_least16_t Ê int_least32_t uint_least32_t int_fast8_t int_fast16_t ¯ uint_fast8_t uint_fast16_t Ê int_fast32_t uint_fast32_t uintptr_t ô intptr_t Ý int64_t « uint64_t » int_least64_t « uint_least64_t » int_fast64_t « uint_fast64_t » intmax_t « uintmax_t » ª ADI_CORE_ENABLE_SUCCESS ADI_CORE_ENABLE_INVALID_CORE ADI_CORE_ENABLE_CURRENT_CORE ADI_CORE_ENABLE_STATUS H ã ADI_CORE_SHARC0 ADI_CORE_ID Ç i _adiCacheStatus adi_cache_success adi_cache_unsuitable_rr adi_cache_anom_rr_fail adi_cache_failure adiCacheStatus õ _adiRangeReg adi_cache_rr0 adi_cache_rr1 adi_cache_rr2 adi_cache_rr3 adi_cache_rr4 adi_cache_rr5
adi_cache_rr6 adi_cache_rr7 adiRangeReg ~ Å _adiRangeSetting adi_cache_disable_range adi_cache_noncacheable_range adi_cache_flush_range adi_cache_lock_range adi_cache_wt_range adiRangeSetting . ó __builtin_quad acc80 Û size_t ptrdiff_t Ý fpos_t
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ß
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quot # rem # ldiv_t º
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quot 0 # rem 0 # lldiv_t ì
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( _t_atexit_fp T Ý f f _t_compare_fp ; errno_t Ý msg N ptr f error h v constraint_handler_t ò SRAM_L2 SRAM_L1 SRAM_DDR SRAM_AUTO MemoryType ½ ? mem_pm mem_dm1 mem_dm2 mem_heap mem_any meml1_sub_type s8 s16 ¯ s32 Ý u8 u16 Ê u32 ô u64 S ufloat ubool q udouble void uvoid ¿ uvoidptr f
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î q name_t à M DAI0_PB01_O DAI0_PB02_O DAI0_PB03_O DAI0_PB04_O DAI0_PB05_O DAI0_PB06_O DAI0_PB07_O DAI0_PB08_O DAI0_PB09_O DAI0_PB10_O DAI0_PB11_O
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DAI0_PB12_O DAI0_PB19_O DAI0_PB20_O DAI1_PB01_O DAI1_PB02_O DAI1_PB03_O DAI1_PB04_O DAI1_PB05_O DAI1_PB06_O DAI1_PB07_O DAI1_PB08_O DAI1_PB09_O DAI1_PB10_O DAI1_PB11_O DAI1_PB12_O DAI1_PB19_O DAI1_PB20_O SPT0_AD0_O SPT0_AD1_O SPT0_BD0_O SPT0_BD1_O SPT1_AD0_O SPT1_AD1_O ! SPT1_BD0_O " SPT1_BD1_O # SPT2_AD0_O $ SPT2_AD1_O % SPT2_BD0_O & SPT2_BD1_O ' SPT3_AD0_O ( SPT3_AD1_O ) SPT3_BD0_O * SPT3_BD1_O + SPT4_AD0_O , SPT4_AD1_O - SPT4_BD0_O . SPT4_BD1_O / SPT5_AD0_O 0 SPT5_AD1_O 1 SPT5_BD0_O 2 SPT5_BD1_O 3 SPT6_AD0_O 4 SPT6_AD1_O 5 SPT6_BD0_O 6 SPT6_BD1_O 7 SPT7_AD0_O 8 SPT7_AD1_O 9 SPT7_BD0_O : SPT7_BD1_O ; PCG_CLKA_O < PCG_CLKB_O = PCG_CLKC_O > PCG_CLKD_O ? PCG_FSA_O À PCG_FSB_O Á PCG_FSC_O Â PCG_FSD_O Ã SRC0_DAT_OP_O Ä SRC0_TDM_IP_O Å SRC1_DAT_OP_O Æ SRC1_TDM_IP_O Ç SRC2_DAT_OP_O È SRC2_TDM_IP_O É SRC3_DAT_OP_O Ê SRC3_TDM_IP_O Ë LOGIC_LOW Ì LOGIC_HIGH Í SourceSignalCount Î SourceSignal û DAI0_PB01_I DAI0_PB02_I DAI0_PB03_I DAI0_PB04_I DAI0_PB05_I DAI0_PB06_I DAI0_PB07_I DAI0_PB08_I DAI0_PB09_I DAI0_PB10_I DAI0_PB11_I
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DAI0_PB12_I DAI0_PB19_I DAI0_PB20_I DAI1_PB01_I DAI1_PB02_I DAI1_PB03_I DAI1_PB04_I DAI1_PB05_I DAI1_PB06_I DAI1_PB07_I DAI1_PB08_I DAI1_PB09_I DAI1_PB10_I DAI1_PB11_I DAI1_PB12_I DAI1_PB19_I DAI1_PB20_I DAI0_PBEN01_I DAI0_PBEN02_I DAI0_PBEN03_I DAI0_PBEN04_I DAI0_PBEN05_I DAI0_PBEN06_I ! DAI0_PBEN07_I " DAI0_PBEN08_I # DAI0_PBEN09_I $ DAI0_PBEN10_I % DAI0_PBEN11_I & DAI0_PBEN12_I ' DAI0_PBEN19_I ( DAI0_PBEN20_I ) DAI1_PBEN01_I * DAI1_PBEN02_I + DAI1_PBEN03_I , DAI1_PBEN04_I - DAI1_PBEN05_I . DAI1_PBEN06_I / DAI1_PBEN07_I 0 DAI1_PBEN08_I 1 DAI1_PBEN09_I 2 DAI1_PBEN10_I 3 DAI1_PBEN11_I 4 DAI1_PBEN12_I 5 DAI1_PBEN19_I 6 DAI1_PBEN20_I 7 SPT0_ACLK_I 8 SPT0_BCLK_I 9 SPT0_AFS_I : SPT0_BFS_I ; SPT0_AD0_I < SPT0_AD1_I = SPT0_BD0_I > SPT0_BD1_I ? SPT1_ACLK_I À SPT1_BCLK_I Á SPT1_AFS_I Â SPT1_BFS_I Ã SPT1_AD0_I Ä SPT1_AD1_I Å SPT1_BD0_I Æ SPT1_BD1_I Ç SPT2_ACLK_I È SPT2_BCLK_I É SPT2_AFS_I Ê SPT2_BFS_I Ë SPT2_AD0_I Ì SPT2_AD1_I Í SPT2_BD0_I Î SPT2_BD1_I Ï SPT3_ACLK_I Ð SPT3_BCLK_I Ñ SPT3_AFS_I Ò SPT3_BFS_I Ó SPT3_AD0_I Ô SPT3_AD1_I Õ SPT3_BD0_I Ö SPT3_BD1_I × SPT4_ACLK_I Ø SPT4_BCLK_I Ù SPT4_AFS_I Ú SPT4_BFS_I Û SPT4_AD0_I Ü SPT4_AD1_I Ý SPT4_BD0_I Þ SPT4_BD1_I ß SPT5_ACLK_I à SPT5_BCLK_I á SPT5_AFS_I â SPT5_BFS_I ã SPT5_AD0_I ä SPT5_AD1_I å SPT5_BD0_I æ SPT5_BD1_I ç SPT6_ACLK_I è SPT6_BCLK_I é SPT6_AFS_I ê SPT6_BFS_I ë SPT6_AD0_I ì SPT6_AD1_I í SPT6_BD0_I î SPT6_BD1_I ï SPT7_ACLK_I ð SPT7_BCLK_I ñ SPT7_AFS_I ò SPT7_BFS_I ó SPT7_AD0_I ô SPT7_AD1_I õ SPT7_BD0_I ö SPT7_BD1_I ÷ PCG_EXTA_I ø PCG_EXTB_I ù PCG_EXTC_I ú PCG_EXTD_I û SRC0_CLK_IP_I ü SRC0_FS_IP_I ý SRC0_DAT_IP_I þ SRC0_CLK_OP_I ÿ SRC0_FS_OP_I SRC0_TDM_OP_I SRC1_CLK_IP_I SRC1_FS_IP_I SRC1_DAT_IP_I SRC1_CLK_OP_I
SRC1_FS_OP_I SRC1_TDM_OP_I SRC2_CLK_IP_I SRC2_FS_IP_I SRC2_DAT_IP_I SRC2_CLK_OP_I SRC2_FS_OP_I SRC2_TDM_OP_I SRC3_CLK_IP_I SRC3_FS_IP_I SRC3_DAT_IP_I SRC3_CLK_OP_I SRC3_FS_OP_I SRC3_TDM_OP_I DestSignalCount DestSignal ` ì SportDef spid ¯ # enable ¯ #enable_sec ¯ #interrupt ¯ #rx ¯ #opmode ¯ #
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clke ¯ # lfs ¯ #mfd ¯ #slots ¯ #vld ¯ #vld_b ¯ # ] PCGDef enable ¯ # opmode ¯ #invert ¯ #width ¯ #sclk_div ¯ #fs_div ¯ #
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SRCDef enable ¯ # format ¯ #wordLen ¯ #ratio ¯ # Ý RouteDef source Ê # dest Ê # R DSPConfig mDualDsp Ê # mDspIndex Ê #mLevelReportInt Ê #mLocalTxNum Ê #mDanteRxNum Ê #mDanteTxNum Ê #
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B ] srcs 4 #Ð DMARegs DMARegsDef R sport_regs X¢ ctl # div #mctl #cs0 # cs1 #cs2 #cs3 #
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# I DMA_Desc next $ # buffer f # I £ sport_enable regs ¨ t enable_sec ¥ x £ ò get_sport_regs ¨ sportid ¢ t à sport_config regs ¨ X config ñ \ i ` dma ë d desca_0 $ h desca_1 $ l dmaBufferLen p dmaBuffer_ping à t dmaBuffer_pong à x g ] æ & SAMPLE_NUM ô mCodecNum z mAudioCodec ! sp_desc ! gSports }!
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..\drv\ D:\project\plugscard\dsp21569\DSP-21569\system D:\project\plugscard\dsp21569\DSP-21569\lib\zlib D:\project\plugscard\dsp21569\DSP-21569\inc C:\Analog Devices\CrossCore Embedded Studio 2.11.0\SHARC\include C:\Analog Devices\CrossCore Embedded Studio 2.11.0\SHARC\include\sys\ ..\drv\sport.c ñøþ¥Æsys\platform.h è¿þ platform_include.h Ô¦µ>cdef21569.h Ü¿ sys\ADSP-2156x-core_cdef.h è¿×istdint.h ì¿ÿMyvals.h ä¿Ç¤ADSP-2156x-core.h è¿·
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def21569.h Ü¿Î.sys\ADSP_2156x_HPC.h æ¿ë
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stdio.h Ü¿ÝCstdio_21xxx.h ä¿stdlib.h ä¿Ustdlib_21xxx.h Ü¿ö.adi_initialize.h ±¾ímemory.h æÚþ¥ßsport.h Á®×¥ typedefs.h ìºÅboard.h Éܧ¢sru_dai.h ª¤ dma.h äÚ¥³config.h Óܧ
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p ©! T sport_enable ® get_sport_regs ò sport_config ÷ SAMPLE_NUM ! mCodecNum .! mAudioCodec , ! = & i - > G p K à K áI K ãJ K J W l o m x C D v à áI ãJ J E f n ¤ à ¤ áI ¤ ãJ ¤ J ª F ¸ s À r Æ s Ì r Õ s Û r ä s ê r ó s ù r s r s s D o H à H áI H ãJ H J t G { H ? B ° A Ê @ ÿR ÿZ g ÿ< k ÿ ÿ ÿ Ã ÿ: Ç ÿ è ÿ ì ÿ ÿ; ÿ 3 ÿ6 7 ÿ n à8 n à; n ãJ n ÿJ à9 à; ãJ ÿJ à à; ãJ ÿJ ¼ à ¼ à; ¼ ãJ ¼ ÿJ Ù à Ù à; Ù ãJ Ù ÿJ
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M ÿ W ÿ: c ÿ m ÿ w ÿ+ ÿ5 ÿ ÿ; ¡ ÿ6 « ÿ7 µ ÿ8 ¿ ÿ9 Ç ÿ Ï ÿ Ù ÿ ã ÿ í ÿ ÷ ÿ ÿ ÿ ÿ ÿ ÿ % ÿ / ÿ 7 ÿ ? ÿ G ÿ O ÿ W ÿ _ ÿ g ÿ o ÿ w ÿ! ÿ" ÿ# ÿ$ ÿ% ¡ ÿ& « ÿ' ³ ÿ( » ÿ) Å ÿ* Ï ÿ, Ù ÿ- ã ÿ. í ÿ/ õ ÿ0 ÿ ÿ1 ÿ2 ÿ3 ÿ4 ) ÿ ÿX ÿX ÿ< à à< ãJ ÿJ ÿ: à à: ãJ ÿJ ÿ; $ à $ à; $ ãJ $ ÿJ À Ã H ` C:\Analog Devices\CrossCore Embedded Studio 2.11.0\easm21k.exe -proc ADSP-21569 -si-revision any -D__WORKAROUND_20000002 -D__WORKAROUND_20000069 -D__WORKAROUNDS_ENABLED -DCORE0=1 -I D:\project\plugscard\dsp21569\DSP-21569\system -I D:\project\plugscard\dsp21569\DSP-21569\lib\zlib -I D:\project\plugscard\dsp21569\DSP-21569\inc -char-size-8 -swc -D__SHORT_WORD_CODE__ -file-attr ProjectName=DSP-21569 -sp -no-source-dependency -o drv\sport.doj C:\Users\86189\AppData\Local\Temp\accaef40d73000\accaef40d73001.s -I D:\project\plugscard\dsp21569\DSP-21569\Debug\..\drv -W2023 -Wsuppress 2548 -Wsuppress 2548 ProjectName DSP-21569 ProjectName DSP-21569 FuncName sport_enable. FuncName get_sport_regs. FuncName llabs. FuncName llmin. FuncName llmax. FuncName sport_config. Encoding SW Content CodeData A^ AnonADI ADSP-21569 dÿÿ 4 Á õ p m e ª 3 P 0 , x \ ©! ¥ 5 0 ¾ 5; t ì ©; 0 & Ù; X U 1> Ô g @ y B ¥B À 5 p eC E p qC T ¤ ÅC _ $F Á ± p åF _
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