/*
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** ADSP-21569 linker description file generated on Aug 02, 2023 at 21:46:12.
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*/
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/*
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** Copyright (C) 2000-2022 Analog Devices Inc., All Rights Reserved.
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**
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** This file is generated automatically based upon the options selected
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** in the System Configuration utility. Changes to the LDF configuration
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** should be made by modifying the appropriate options rather than editing
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** this file. To access the System Configuration utility, double-click the
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** system.svc file from a navigation view.
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**
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** Custom additions can be inserted within the user-modifiable sections. These
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** sections are bounded by comments that start with "$VDSG". Only changes
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** placed within these sections are preserved when this file is re-generated.
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**
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** Product : CrossCore Embedded Studio
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** Tool Version : 6.2.3.3
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*/
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ARCHITECTURE(ADSP-21569)
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/*
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** Define a linked library list. Libraries from the command line are included
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** in COMMAND_LINE_OBJECTS.
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*/
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$LIBRARIES =
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/*$VDSG<insert-user-libraries-at-beginning> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-libraries-at-beginning> */
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libcc.dlb
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,libc.dlb
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,libio.dlb
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,libcpp.dlb
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,libosal_noos.dlb
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,libprofile.dlb
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,libssl.dlb
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,libdrv.dlb
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,libdsp.dlb
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,libldr.dlb
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/*$VDSG<insert-user-libraries-at-end> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-libraries-at-end> */
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;
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/*
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** Define a linked objects list.
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*/
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$OBJECTS =
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/*$VDSG<insert-user-objects-at-beginning> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-objects-at-beginning> */
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"app_startup.doj"
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,$COMMAND_LINE_OBJECTS
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/*$VDSG<insert-user-objects-at-end> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-objects-at-end> */
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;
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/*
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** List of all objects and libraries.
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*/
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$OBJS_LIBS = $OBJECTS, $LIBRARIES;
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/*
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** List of objects and libraries which prefer internal memory as
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** specified by prefersMem attribute.
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*/
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$OBJS_LIBS_INTERNAL =
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/*$VDSG<insert-libraries-internal> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-libraries-internal> */
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$OBJS_LIBS{prefersMem("internal")}
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/*$VDSG<insert-libraries-internal-end> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-libraries-internal-end> */
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;
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/*
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** List of objects and libraries which don't have a preference for
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** external memory as specified by prefersMem attribute.
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*/
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$OBJS_LIBS_NOT_EXTERNAL =
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/*$VDSG<insert-libraries-not-external> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-libraries-not-external> */
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$OBJS_LIBS{!prefersMem("external")}
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/*$VDSG<insert-libraries-not-external-end> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-libraries-not-external-end> */
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;
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/*$VDSG<insert-user-macros> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-macros> */
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MEMORY
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{
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// ADSP-21569 MEMORY MAP.
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// The ADSP-2156x SHARC+ cores have 5 Mbit L1 RAM split over four blocks.
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// This LDF defines memory sections only in byte format. It is no longer
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// necessary to partition memory for different widths and different
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// input types.
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// The output sections that populate the memory are defined to use
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// one of the following qualifiers:
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// BW - byte sections
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// PM - PM data/ISA code
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// DM - DM data
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// SW - VISA code
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// DATA64 - long word data
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// The linker filters the inputs for each output section to match
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// these output section qualfiers. Each output section uses the same
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// byte memory sections which the linker packs correctly for each
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// qualifier.
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// Notes:
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// 1) The interrupt Vector Table (IVT) code is placed in internal memory
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// by default and has to use ISA (NW, 48 bit) instructions.
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// ----------------------- L1-Block 0 RAM (1.5 MBit) ------------------------
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mem_iv_code { TYPE(PM RAM) START(0x00090000) END(0x000900a7) WIDTH(48) }
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mem_block0_bw { TYPE(BW RAM) START(0x002403f0) END(0x0026ffff) WIDTH(8) }
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// ----------------------- L1-Block 1 RAM (1.5 MBit) ------------------------
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// The data cache attached to block 1 caches all the external memory access
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// requests for the DM bus. The size of the cache can be adjusted with a
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// corresponding reduction of the available non-cache L1 space.
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// 64 KB at the end of block 1 is DM cache
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mem_block1_bw { TYPE(BW RAM) START(0x002c0000) END(0x002dffff) WIDTH(8) }
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// ----------------------- L1-Block 2 RAM (1 MBit) --------------------------
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// The data cache attached to block 2 caches all the external memory access
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// requests for the PM bus. If the size of the cache is 128KB, the whole
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// of block 2 is cache.
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// 32 KB at the end of block 2 is PM cache
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mem_block2_bw { TYPE(BW RAM) START(0x00300000) END(0x00317fff) WIDTH(8) }
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// ----------------------- L1-Block 3 RAM (1 MBit) --------------------------
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// The instruction cache is attached to block 3.
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// 32 KB at the end of block 3 is instruction cache
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mem_block3_bw { TYPE(BW RAM) START(0x00380000) END(0x00397fff) WIDTH(8) }
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// ----------------------- L2-RAM (8 MBit) ----------------------------------
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// The 8Mb/1MB L2 SRAM memory has 8 contiguous 128 KB banks.
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//
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// Notes:
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// 1. The boot code claims the last 8KB of L2 SRAM, as working space.
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// This memory is not bootable, but can be used by the application once
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// booting is complete (NO_INIT in CCES). Note that if the application
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// makes use of this space and then calls the Boot Code APIs, the
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// space may be corrupted.
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// 2. All memory except the 16KB before the boot code claimed L2 SRAM
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// is cached.
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mem_L2_bw { TYPE(BW RAM) START(0x20000000) END(0x200f9fff) WIDTH(8) }
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mem_L2UC_bw { TYPE(BW RAM) START(0x200fa000) END(0x200fdfff) WIDTH(8) }
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mem_L2BC_bw { TYPE(BW RAM) START(0x200fe000) END(0x200fffff) WIDTH(8) }
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#define MY_L2_UNCACHED_MEM mem_L2UC_bw
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#define MY_L2_CACHED_MEM mem_L2_bw
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// ----------------------- L3 -----------------------------------------------
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// DMC0 DDR3 SDRAM memory.
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//
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// Notes
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// 1. Code execution addresses are restricted for SHARC cores so
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// the memory allocated cannot be increased or moved.
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// 2. All L3 will be considered cached.
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// 3. MY_SDRAM_DATA1_MEM is defined to be the smaller L3 data section and
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// MY_SDRAM_DATA2_MEM is the larger one.
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// 4. The reason for splitting the SDRAM into segments is that the SW
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// alias doesn't start at the bottom of the DMC address range and the
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// linker doesn't support trying to allocate from the parts of a larger
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// BW segment that might include a smaller SW alias range.
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// 5. The stack in SDRAM does not use memory in byte range 0xA0000000
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// through to 0xBFFFFFFF as these addresses cannot be converted to
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// word-addresses.
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// ----------------------- 256MB DMC0(DDR-A) --------------------------------
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// 256MB DMC0 DDR3 SDRAM memory is partitioned and used as follows:
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// DDR-A segment 1 : 6MB NW code or data
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// 4MB data
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// DDR-A segment 2 : 6MB VISA code or data
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// 240MB data
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mem_DMC0_SDRAM_A1 { TYPE(BW RAM) START(0x80000000) END(0x809fffff) WIDTH(8) }
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mem_DMC0_SDRAM_A2 { TYPE(BW RAM) START(0x80a00000) END(0x8fffffff) WIDTH(8) }
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#define MY_SDRAM_NWCODE_MEM mem_DMC0_SDRAM_A1
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#define MY_SDRAM_DATA1_MEM mem_DMC0_SDRAM_A1
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#define MY_SDRAM_SWCODE_MEM mem_DMC0_SDRAM_A2
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#define MY_SDRAM_DATA2_MEM mem_DMC0_SDRAM_A2
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#define SDRAM_STACK_HEAP_BLOCK mem_DMC0_SDRAM_A2
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/*$VDSG<insert-new-memory-segments> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-memory-segments> */
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} /* MEMORY */
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PROCESSOR 21569_CORE0_SHARC0
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{
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LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST )
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OUTPUT($COMMAND_LINE_OUTPUT_FILE)
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KEEP(___ctor_NULL_marker)
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KEEP(__ctor_NULL_marker.)
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ENTRY(start)
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/*$VDSG<insert-user-ldf-commands> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-user-ldf-commands> */
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SECTIONS
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{
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/*$VDSG<insert-new-sections-at-iv_code> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-iv_code> */
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// ------------------------------------------------------------------
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// Block 0 is primarily used for the interrupt vectors code, stack,
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// heap and DM data.
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// If the entire block3 is cache (128KB size) it also includes priority
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// code section.
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/*$VDSG<insert-new-sections-for-l1_block0> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-for-l1_block0> */
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#define IV_CODE dxe_iv_code
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IV_CODE PM
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{
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/*$VDSG<insert-new-sections-at-the-start-of-iv_code> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-start-of-iv_code> */
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// Interrupt vector code (4 NW instructions per interrupt)
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INPUT_SECTIONS( $OBJECTS(iv_code) )
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/*$VDSG<insert-new-sections-at-the-end-of-iv_code> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-end-of-iv_code> */
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} > mem_iv_code
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/*$VDSG<insert-new-sections-at-mem_block0_bw> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-mem_block0_bw> */
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// Stack and heap initial memory reserve.
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dxe_block0_stack_and_heap_reserve NO_INIT BW
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{
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RESERVE(heaps_and_system_stack_in_L1, heaps_and_system_stack_in_L1_length = 189440, 8)
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} > mem_block0_bw
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// Highest priority (prio0) data and code.
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dxe_block0_data_prio0_bw BW
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{
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// Highest priority byte data for block0.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0 seg_int_data) )
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} > mem_block0_bw
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dxe_block0_data_prio0 DM
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{
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// Highest priority data for block 0.
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0 seg_int_data ) )
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} > mem_block0_bw
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dxe_block0_sw_code_prio0 SW
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{
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// Highest priority SW code for block 0.
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INPUT_SECTION_ALIGN(2)
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/*$VDSG<insert-new-sections-at-the-start-of-dxe_block0_sw_code_prio0> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-start-of-dxe_block0_sw_code_prio0> */
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FILL(0x1) // fill gaps in memory with NOPs
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0) )
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/*$VDSG<insert-new-sections-at-the-end-of-dxe_block0_sw_code_prio0> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-end-of-dxe_block0_sw_code_prio0> */
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} > mem_block0_bw
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dxe_block0_nw_code_prio0 PM
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{
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// Highest priority code for block 0.
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INPUT_SECTION_ALIGN(2)
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/*$VDSG<insert-new-sections-at-the-start-of-dxe_block0_nw_code_prio0> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-start-of-dxe_block0_nw_code_prio0> */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0) )
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/*$VDSG<insert-new-sections-at-the-end-of-dxe_block0_nw_code_prio0> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-end-of-dxe_block0_nw_code_prio0> */
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} > mem_block0_bw
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dxe_block0_noinit_prio0 NO_INIT DM
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{
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// Highest priority uninitialized data.
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0_noinit_data seg_int_noinit_data) )
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} > mem_block0_bw
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dxe_block0_noinit_prio0_bw NO_INIT BW
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{
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// Highest priority uninitialized data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0_noinit_data seg_int_noinit_data) )
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} > mem_block0_bw
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dxe_block0_bsz_prio0 ZERO_INIT DM
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{
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// Highest priority zero initialized data.
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0_bsz_data seg_int_bsz_data) )
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} > mem_block0_bw
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dxe_block0_bsz_prio0_bw ZERO_INIT BW
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{
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// Highest priority zero initialized data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block0_bsz_data seg_int_bsz_data) )
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} > mem_block0_bw
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// High priority (prio1) data, and code if necessary.
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dxe_block0_data_prio1 DM
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{
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// High priority data.
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda_nw seg_dmda seg_vtbl) )
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} > mem_block0_bw
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dxe_block0_data_prio1_bw BW
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{
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// High priority byte data for block0.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda_bw seg_dmda seg_vtbl) )
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} > mem_block0_bw
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dxe_block0_bsz_prio1 ZERO_INIT DM
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{
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// High priority zero initialized data.
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_bsz_data .bss32 .bss bsz) )
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} > mem_block0_bw
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dxe_block0_bsz_prio1_bw ZERO_INIT BW
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{
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// High priority zero initialized data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_bsz_data .bss8 .bss) )
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} > mem_block0_bw
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dxe_block0_noinit_prio1 NO_INIT DM
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{
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// High priority uninitialized data.
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_noinit_data) )
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} > mem_block0_bw
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dxe_block0_noinit_prio1_bw NO_INIT BW
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{
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// High priority uninitialized data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_noinit_data) )
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} > mem_block0_bw
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// Next map data that's not thought to be low priority.
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dxe_block0_data_prio2 DM
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{
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// Default priority data.
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda_nw seg_dmda seg_vtbl) )
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} > mem_block0_bw
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dxe_block0_data_prio2_bw BW
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{
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// Default priority data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda_bw seg_dmda seg_vtbl) )
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} > mem_block0_bw
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dxe_block0_bsz_prio2 ZERO_INIT DM
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{
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// Default priority zero initialized data.
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_bsz_data .bss32 .bss bsz) )
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} > mem_block0_bw
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dxe_block0_bsz_prio2_bw ZERO_INIT BW
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{
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// Default priority zero initialized data.
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INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_bsz_data .bss8 .bss) )
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} > mem_block0_bw
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dxe_block0_noinit_prio2 NO_INIT DM
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{
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// Default priority uninitialized data.
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_noinit_data) )
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} > mem_block0_bw
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dxe_block0_noinit_prio2_bw NO_INIT BW
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{
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// Default priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_noinit_data) )
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} > mem_block0_bw
|
|
dxe_block0_data_prio3 DM
|
{
|
// Unspecified and lowest priority data for any unused memory.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_block0_bw
|
|
dxe_block0_data_prio3_bw BW
|
{
|
// Unspecified and lowest priority data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > mem_block0_bw
|
|
dxe_block0_bsz_prio3 ZERO_INIT DM
|
{
|
// Unspecified and lowest priority zero init data for any unused memory.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_bsz_data .bss32 .bss) )
|
} > mem_block0_bw
|
|
dxe_block0_bsz_prio3_bw ZERO_INIT BW
|
{
|
// Unspecified and lowest priority zero init data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_bsz_data .bss8 .bss) )
|
} > mem_block0_bw
|
|
dxe_block0_noinit_prio3 NO_INIT DM
|
{
|
// Unspecified and lowest priority no init data for any unused memory.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_noinit_data) )
|
} > mem_block0_bw
|
|
dxe_block0_noinit_prio3_bw NO_INIT BW
|
{
|
// Unspecified and lowest priority no init data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_noinit_data) )
|
} > mem_block0_bw
|
|
|
// ------------------------------------------------------------------
|
// Block 1 is primarily used for the DM data and DM cache.
|
|
// Define a DM cache size symbol.
|
// The values used match the bits in the L1C0_CFG register size bits or
|
// -1 if cache is off.
|
|
___ldf_dmcachesize = 2; // 64 KB DM cache
|
|
/*$VDSG<insert-new-sections-for-l1_block1> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-for-l1_block1> */
|
|
dxe_block1_data_prio0_bw BW
|
{
|
// Highest priority byte data for block1.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1 seg_int_data) )
|
} > mem_block1_bw
|
|
dxe_block1_data_prio0 DM
|
{
|
// Highest priority data for block1.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio0> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio0> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1 seg_int_data) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio0> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio0> */
|
|
} > mem_block1_bw
|
|
dxe_block1_sw_code_prio0 SW
|
{
|
// Highest priority SW code for block1.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1) )
|
} > mem_block1_bw
|
|
dxe_block1_nw_code_prio0 PM
|
{
|
// Highest priority code for block1.
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio0 NO_INIT DM
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1_noinit_data seg_int_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio0_bw NO_INIT BW
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1_noinit_data seg_int_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio0 ZERO_INIT DM
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1_bsz_data seg_int_bsz_data) )
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio0_bw ZERO_INIT BW
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block1_bsz_data seg_int_bsz_data) )
|
} > mem_block1_bw
|
|
dxe_block1_data_prio1 DM
|
{
|
// High priority data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio1> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio1> */
|
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda_nw seg_dmda seg_vtbl) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio1> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio1> */
|
|
} > mem_block1_bw
|
|
dxe_block1_data_prio1_bw BW
|
{
|
// High priority byte data for block1.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda_bw seg_dmda seg_vtbl) )
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio1 ZERO_INIT DM
|
{
|
// High priority zero initialized data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio1> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio1> */
|
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_bsz_data .bss32 .bss bsz) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio1> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio1> */
|
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio1_bw ZERO_INIT BW
|
{
|
// High priority zero initialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_bsz_data .bss8 .bss) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio1 NO_INIT DM
|
{
|
// High priority uninitialized data.
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio1_bw NO_INIT BW
|
{
|
// High priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_data_prio2 DM
|
{
|
// Default priority data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio2> */
|
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda_nw seg_dmda seg_vtbl) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio2> */
|
|
} > mem_block1_bw
|
|
dxe_block1_data_prio2_bw BW
|
{
|
// Default priority data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda_bw seg_dmda seg_vtbl) )
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio2 ZERO_INIT DM
|
{
|
// Default priority zero initialized data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio2> */
|
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_bsz_data .bss32 .bss bsz) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio2> */
|
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio2_bw ZERO_INIT BW
|
{
|
// Default priority zero initialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_bsz_data .bss8 .bss) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio2 NO_INIT DM
|
{
|
// Default priority uninitialized data.
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio2_bw NO_INIT BW
|
{
|
// Default priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_data_prio3 DM
|
{
|
// Unspecified and lowest priority data for any unused memory.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio3> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_dm_data_prio3> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio3> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_dm_data_prio3> */
|
|
} > mem_block1_bw
|
|
dxe_block1_data_prio3_bw BW
|
{
|
// Unspecified and lowest priority data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio3 ZERO_INIT DM
|
{
|
// Unspecified and lowest priority zero init data for any unused memory.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio3> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_bsz_prio3> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_bsz_data .bss32 .bss) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio3> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_bsz_prio3> */
|
|
} > mem_block1_bw
|
|
dxe_block1_bsz_prio3_bw ZERO_INIT BW
|
{
|
// Unspecified and lowest priority zero init data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_bsz_data .bss8 .bss) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio3 NO_INIT DM
|
{
|
// Unspecified and lowest priority no init data for any unused memory.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_noinit_data) )
|
} > mem_block1_bw
|
|
dxe_block1_noinit_prio3_bw NO_INIT BW
|
{
|
// Unspecified and lowest priority no init data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_noinit_data) )
|
} > mem_block1_bw
|
|
|
// ------------------------------------------------------------------
|
// Block 2 is primarily used for the PM data and PM cache.
|
|
// Define a PM cache size symbol.
|
// The values used match the bits in the L1C0_CFG register size bits or
|
// -1 if cache is off.
|
|
___ldf_pmcachesize = 1; // 32 KB PM cache
|
|
/*$VDSG<insert-new-sections-for-l1_block2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-for-l1_block2> */
|
|
dxe_block2_data_prio0_bw BW
|
{
|
// Highest priority byte data for block2.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2) )
|
} > mem_block2_bw
|
|
dxe_block2_data_prio0 DM
|
{
|
// Highest priority data for block2.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2) )
|
} > mem_block2_bw
|
|
dxe_block2_sw_code_prio0 SW
|
{
|
// Highest priority SW code for block2.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2) )
|
} > mem_block2_bw
|
|
dxe_block2_nw_code_prio0 PM
|
{
|
// Highest priority code for block2.
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2) )
|
} > mem_block2_bw
|
|
dxe_block2_noinit_prio0 NO_INIT DM
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2_noinit_data) )
|
} > mem_block2_bw
|
|
dxe_block2_noinit_prio0_bw NO_INIT BW
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2_noinit_data) )
|
} > mem_block2_bw
|
|
dxe_block2_bsz_prio0 ZERO_INIT DM
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2_bsz_data) )
|
} > mem_block2_bw
|
|
dxe_block2_bsz_prio0_bw ZERO_INIT BW
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block2_bsz_data) )
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio1 PM 32
|
{
|
// High priority pm data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_pm_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_pm_data> */
|
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_pmda_nw seg_pmda) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_pm_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_pm_data> */
|
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio1_bw BW
|
{
|
// High priority data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_pmda_bw seg_pmda) )
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio2 PM 32
|
{
|
// Default priority pm data.
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_pmda_nw seg_pmda) )
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio2_bw BW
|
{
|
// Default priority pm data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_pmda_bw seg_pmda) )
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio3 PM 32
|
{
|
// Unspecified and lowest priority pm data for any unused memory.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_nw seg_pmda) )
|
} > mem_block2_bw
|
|
dxe_block2_pm_data_prio3_bw BW
|
{
|
// Unspecified and lowest priority pm data for any unused memory.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda) )
|
} > mem_block2_bw
|
|
|
// ------------------------------------------------------------------
|
// Block 3 is primarily used for code and instruction cache.
|
|
// Define an instruction cache size symbol.
|
// The values used match the bits in the L1C0_CFG register size bits or
|
// -1 if cache is off.
|
|
___ldf_icachesize = 1; // 32 KB instruction cache
|
|
/*$VDSG<insert-new-sections-for-l1_block3> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-for-l1_block3> */
|
|
dxe_block3_data_prio0 DM
|
{
|
// Highest priority data for block3.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3) )
|
} > mem_block3_bw
|
|
dxe_block3_data_prio0_bw BW
|
{
|
// Highest priority byte data for block3.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3) )
|
} > mem_block3_bw
|
|
dxe_block3_noinit_prio0 NO_INIT DM
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3_noinit_data) )
|
} > mem_block3_bw
|
|
dxe_block3_noinit_prio0_bw NO_INIT BW
|
{
|
// Highest priority uninitialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3_noinit_data) )
|
} > mem_block3_bw
|
|
dxe_block3_bsz_prio0 ZERO_INIT DM
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3_bsz_data) )
|
} > mem_block3_bw
|
|
dxe_block3_bsz_prio0_bw ZERO_INIT BW
|
{
|
// Highest priority zero initialized data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3_bsz_data) )
|
} > mem_block3_bw
|
|
// Now use the remaining block 3 memory for code sections.
|
// Starting with inputs sections required to be in internal memory.
|
dxe_block3_sw_code_prio0 SW
|
{
|
// Highest priority SW code for block3.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3 seg_int_code_sw seg_int_code) )
|
} > mem_block3_bw
|
|
dxe_block3_nw_code_prio0 PM
|
{
|
// Highest priority code for block3.
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l1_block3 seg_int_code) )
|
// The __lib_setup_memory routine requires seg_init to be placed in L1.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_init) )
|
} > mem_block3_bw
|
|
// Try and use internal memory for the highest priority code.
|
// Inputs that are not prioritized can use L2 or L3.
|
dxe_block3_sw_code_prio1 SW
|
{
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_swco seg_pmco) )
|
} > mem_block3_bw
|
|
dxe_block3_nw_code_prio1 PM
|
{
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_pmco) )
|
} > mem_block3_bw
|
|
dxe_block3_sw_code_prio2 SW
|
{
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_swco seg_pmco) )
|
} > mem_block3_bw
|
|
dxe_block3_nw_code_prio2 PM
|
{
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_pmco) )
|
} > mem_block3_bw
|
|
#define BLOCK3_SW_CODE dxe_block3_sw_code_prio3
|
BLOCK3_SW_CODE SW
|
{
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_swco seg_pmco) )
|
} > mem_block3_bw
|
|
#define BLOCK3_NW_CODE dxe_block3_nw_code_prio3
|
BLOCK3_NW_CODE PM
|
{
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmco) )
|
} > mem_block3_bw
|
|
|
// ------------------------------------------------------------------
|
// Input any unmapped data or code to fill up any unused L1 memory
|
// available in the blocks. However, we can't put code in blocks 1 and
|
// 2 when they are used as data caches.
|
|
|
/*$VDSG<insert-new-sections-at-mem_block2_overflow> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-at-mem_block2_overflow> */
|
|
// try code in blocks 0-2
|
dxe_block0_sw_code SW
|
{
|
// VISA code.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_code_sw seg_int_code seg_swco seg_pmco) )
|
} > mem_block0_bw
|
|
dxe_block0_nw_code PM
|
{
|
// ISA code.
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_code) )
|
// The __lib_setup_memory routine requires seg_init to be placed in L1.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_init) )
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmco) )
|
} > mem_block0_bw
|
|
|
// next try non-PM data in block 2
|
|
dxe_block2_data DM
|
{
|
// general data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_overflow_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_overflow_data> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_data seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_overflow_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_overflow_data> */
|
|
} > mem_block2_bw
|
|
dxe_block2_data_bw BW
|
{
|
// General data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_data seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > mem_block2_bw
|
|
dxe_block2_bsz ZERO_INIT DM
|
{
|
// Zero init data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_bsz> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block2_bsz> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_bsz_data seg_bsz_data .bss32 .bss) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_bsz> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block2_bsz> */
|
|
} > mem_block2_bw
|
|
dxe_block2_bsz_bw ZERO_INIT BW
|
{
|
// Zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_bsz_data seg_bsz_data .bss8 .bss) )
|
} > mem_block2_bw
|
|
dxe_block2_noinit NO_INIT DM
|
{
|
// No-init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_noinit_data seg_noinit_data) )
|
} > mem_block2_bw
|
|
dxe_block2_noinit_bw NO_INIT BW
|
{
|
// No-init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_noinit_data seg_noinit_data) )
|
} > mem_block2_bw
|
|
// next try PM data in block 0 and block 1
|
dxe_block0_pm_data PM 32
|
{
|
// PM data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_nw seg_pmda) )
|
} > mem_block0_bw
|
|
dxe_block0_pm_data_bw BW
|
{
|
// PM data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_bw seg_pmda) )
|
} > mem_block0_bw
|
|
dxe_block1_pm_data PM 32
|
{
|
// PM data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_overflow_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_block1_overflow_data> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_nw seg_pmda) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_overflow_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_block1_overflow_data> */
|
|
} > mem_block1_bw
|
|
dxe_block1_pm_data_bw BW
|
{
|
// PM data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_bw seg_pmda) )
|
} > mem_block1_bw
|
|
// lastly try DM and PM data in block 3
|
dxe_block3_data DM
|
{
|
// General data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_data seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > mem_block3_bw
|
|
dxe_block3_data_bw BW
|
{
|
// General data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_data seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > mem_block3_bw
|
|
dxe_block3_pm_data PM 32
|
{
|
// PM data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_nw seg_pmda) )
|
} > mem_block3_bw
|
|
dxe_block3_pm_data_bw BW
|
{
|
// PM data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_bw seg_pmda) )
|
} > mem_block3_bw
|
|
dxe_block3_bsz ZERO_INIT DM
|
{
|
// Zero init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_bsz_data seg_bsz_data .bss32 .bss) )
|
} > mem_block3_bw
|
|
dxe_block3_bsz_bw ZERO_INIT BW
|
{
|
// Zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_bsz_data seg_bsz_data .bss8 .bss) )
|
} > mem_block3_bw
|
|
dxe_block3_noinit NO_INIT DM
|
{
|
// No-init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_noinit_data seg_noinit_data) )
|
} > mem_block3_bw
|
|
dxe_block3_noinit_bw NO_INIT BW
|
{
|
// No-init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_int_noinit_data seg_noinit_data) )
|
} > mem_block3_bw
|
|
|
// ------------------------------------------------------------------
|
// L2 - core memory
|
|
|
/*$VDSG<insert-new-sections-for-l2> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-for-l2> */
|
|
// First do inputs for noinit data to the boot code working area memory.
|
dxe_l2bootcode_noinit NO_INIT DM
|
{
|
// L2 no init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
|
} > mem_L2BC_bw
|
|
dxe_l2bootcode_noinit_bw NO_INIT BW
|
{
|
// L2 no init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
|
} > mem_L2BC_bw
|
|
#if defined(MY_L2_CACHED_MEM)
|
dxe_l2_user_tables_nw DM
|
{
|
FORCE_CONTIGUITY
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_l2_user_tables_nw> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_l2_user_tables_nw> */
|
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_user_tables_bw BW
|
{
|
FORCE_CONTIGUITY
|
INPUT_SECTION_ALIGN(4)
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_l2_user_tables_bw> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_l2_user_tables_bw> */
|
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_stack_and_heap_reserve NO_INIT BW
|
{
|
RESERVE(heaps_and_system_stack_in_L2, heaps_and_system_stack_in_L2_length = 1024000, 8)
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_sw_code SW
|
{
|
// VISA code.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_swco seg_swco seg_pmco) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_nw_code PM
|
{
|
// ISA code.
|
INPUT_SECTION_ALIGN(2)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_pmco seg_pmco) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_data DM
|
{
|
// L2 data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_dmda seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_data_bw BW
|
{
|
// L2 data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_dmda_bw seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_bsz ZERO_INIT DM
|
{
|
// L2 zero init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_bsz_data seg_bsz_data .bss32 .bss) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_bsz_bw ZERO_INIT BW
|
{
|
// L2 zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_bsz_data seg_bsz_data .bss8 .bss) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_noinit NO_INIT DM
|
{
|
// L2 no init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_noinit_bw NO_INIT BW
|
{
|
// L2 no init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_pm_data PM 32
|
{
|
// L2 pm data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda_nw seg_pmda) )
|
} > MY_L2_CACHED_MEM
|
|
dxe_l2_pm_data_bw BW
|
{
|
// L2 pm data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_pmda) )
|
} > MY_L2_CACHED_MEM
|
|
#else
|
#warning L2 cached memory unused
|
#endif // MY_L2_CACHED_MEM
|
|
// ------------------------------------------------------------------
|
// L2 - uncached memory
|
|
|
// Define labels used by library cache support functions.
|
___l2_uncached_start = MEMORY_START(mem_L2UC_bw);
|
___l2_uncached_end = MEMORY_END (mem_L2UC_bw);
|
#if defined(MY_L2_UNCACHED_MEM)
|
dxe_l2_uncached_bw BW
|
{
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_uncached seg_uncached) )
|
} > MY_L2_UNCACHED_MEM
|
|
dxe_l2_uncached DM
|
{
|
INPUT_SECTIONS( $OBJS_LIBS(seg_l2_uncached seg_uncached) )
|
} > MY_L2_UNCACHED_MEM
|
|
#else
|
#warning L2 uncached memory unused
|
#endif // MY_L2_UNCACHED_MEM
|
|
// ------------------------------------------------------------------
|
// SDRAM
|
|
|
/*$VDSG<insert-new-sections-for-sdram> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-for-sdram> */
|
|
|
/*$VDSG<insert-new-sections-at-mem_sdram_code> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-at-mem_sdram_code> */
|
|
#if defined(MY_SDRAM_SWCODE_MEM)
|
dxe_sdram_sw_code SW
|
{
|
// VISA code.
|
INPUT_SECTION_ALIGN(2)
|
FILL(0x1) // fill gaps in memory with NOPs
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_sw_code> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_sw_code> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_code seg_swco seg_pmco) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_sw_code> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_sw_code> */
|
|
} > MY_SDRAM_SWCODE_MEM
|
|
#endif // defined(MY_SDRAM_SWCODE_MEM)
|
dxe_sdram_nw_code PM
|
{
|
// ISA code.
|
INPUT_SECTION_ALIGN(2)
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_nw_code> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_nw_code> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_code seg_pmco) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_nw_code> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_nw_code> */
|
|
} > MY_SDRAM_NWCODE_MEM
|
|
|
/*$VDSG<insert-new-sections-at-mem_sdram_dmda> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-at-mem_sdram_dmda> */
|
|
dxe_sdram_user_tables_nw DM
|
{
|
FORCE_CONTIGUITY
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_user_tables_nw> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_user_tables_nw> */
|
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_cpp_ctors_nw DM
|
{
|
// C++ global constructors list for word-addressed code.
|
FORCE_CONTIGUITY
|
__ctors = .; // __ctors points to the start of the section
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ctdm) )
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ctdml) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_cpp_eh_gdt_nw DM
|
{
|
// C++ exceptions data table.
|
FORCE_CONTIGUITY
|
INPUT_SECTIONS( $OBJS_LIBS(.gdt32 .gdt) )
|
INPUT_SECTIONS( $OBJS_LIBS(.gdtl32 .gdtl) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_cpp_eh_gdt_bw BW
|
{
|
// C++ exceptions data table.
|
INPUT_SECTION_ALIGN(4)
|
FORCE_CONTIGUITY
|
INPUT_SECTIONS( $OBJS_LIBS(.gdt) )
|
INPUT_SECTIONS( $OBJS_LIBS(.gdtl) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_cpp_ctors_bw BW
|
{
|
// C++ global constructors list for byte-addressed code.
|
INPUT_SECTION_ALIGN(4)
|
FORCE_CONTIGUITY
|
_ctors. = .; // _ctors. points to the start of the section
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ctdm) )
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ctdml seg_ctdml_bw) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_user_tables_bw BW
|
{
|
FORCE_CONTIGUITY
|
INPUT_SECTION_ALIGN(4)
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_user_tables_bw> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_user_tables_bw> */
|
|
} > MY_SDRAM_DATA1_MEM
|
|
#if defined(MY_SDRAM_DATA2_MEM)
|
dxe_sdram_stack_and_heap_reserve NO_INIT BW
|
{
|
RESERVE(heaps_and_system_stack_in_L3, heaps_and_system_stack_in_L3_length = 134217728, 8)
|
} > MY_SDRAM_DATA2_MEM
|
|
#else
|
dxe_sdram_stack_and_heap_reserve NO_INIT BW
|
{
|
RESERVE(heaps_and_system_stack_in_L3, heaps_and_system_stack_in_L3_length = 134217728, 8)
|
} > MY_SDRAM_DATA1_MEM
|
|
#endif // defined(MY_SDRAM_DATA2_MEM)
|
dxe_sdram_data DM
|
{
|
// general data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_data> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_data seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_data> */
|
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_data_bw BW
|
{
|
// general data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_data seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_bsz ZERO_INIT DM
|
{
|
// zero init data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_bsz> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_bsz> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_bsz_data seg_bsz_data .bss32 .bss) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_bsz> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_bsz> */
|
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_bsz_bw ZERO_INIT BW
|
{
|
// zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_bsz_data seg_bsz_data .bss8 .bss) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_noinit NO_INIT DM
|
{
|
// no init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_noinit_data seg_noinit_data) )
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_noinit_bw NO_INIT BW
|
{
|
// no init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_noinit_data seg_noinit_data) )
|
} > MY_SDRAM_DATA1_MEM
|
|
|
/*$VDSG<insert-new-sections-at-mem_sdram_pmda> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-new-sections-at-mem_sdram_pmda> */
|
|
dxe_sdram_pm_data PM 32
|
{
|
// pm data.
|
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_pm_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_pm_data> */
|
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ext_pmda seg_pmda_nw seg_pmda) )
|
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_pm_data> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<insert-input-sections-at-the-end-of-dxe_sdram_pm_data> */
|
|
} > MY_SDRAM_DATA1_MEM
|
|
dxe_sdram_pm_data_bw BW
|
{
|
// pm data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ext_pmda seg_pmda) )
|
} > MY_SDRAM_DATA1_MEM
|
|
#if defined(MY_SDRAM_DATA2_MEM)
|
dxe_sdram_data2 DM
|
{
|
// general data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_data seg_dmda_nw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_bsz2 ZERO_INIT DM
|
{
|
// zero init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_bsz_data seg_bsz_data .bss32 .bss) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_noinit2 NO_INIT DM
|
{
|
// no init data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_noinit_data seg_noinit_data) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_pm_data2 PM 32
|
{
|
// pm data.
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ext_pmda seg_pmda_nw seg_pmda) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_data2_bw BW
|
{
|
// general data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_data seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_bsz2_bw ZERO_INIT BW
|
{
|
// zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_bsz_data seg_bsz_data .bss8 .bss) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_noinit2_bw NO_INIT BW
|
{
|
// no init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_noinit_data seg_noinit_data) )
|
} > MY_SDRAM_DATA2_MEM
|
|
dxe_sdram_pm_data2_bw BW
|
{
|
// pm data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ext_pmda seg_pmda) )
|
} > MY_SDRAM_DATA2_MEM
|
|
#endif // defined MY_SDRAM_DATA2_MEM
|
|
#if defined(MY_SDRAM_BWONLY_MEM)
|
dxe_sdram_data3_bw BW
|
{
|
// general data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram seg_ext_data seg_dmda_bw seg_dmda seg_vtbl .rtti .cht .edt) )
|
} > MY_SDRAM_BWONLY_MEM
|
|
dxe_sdram_bsz3_bw ZERO_INIT BW
|
{
|
// zero init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_bsz_data seg_bsz_data .bss8 .bss) )
|
} > MY_SDRAM_BWONLY_MEM
|
|
dxe_sdram_noinit3_bw NO_INIT BW
|
{
|
// no init data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_sdram_noinit_data seg_noinit_data) )
|
} > MY_SDRAM_BWONLY_MEM
|
|
dxe_sdram_pm_data3_bw BW
|
{
|
// pm data.
|
INPUT_SECTION_ALIGN(4)
|
INPUT_SECTIONS( $OBJS_LIBS(seg_ext_pmda seg_pmda) )
|
} > MY_SDRAM_BWONLY_MEM
|
|
#endif // defined MY_SDRAM_BWONLY_MEM
|
|
// ------------------------------------------------------------------
|
// Complete the stack and heap definitions.
|
|
|
/*$VDSG<before-completing-the-stack-and-heap-definitions> */
|
/* Text inserted between these $VDSG comments will be preserved */
|
/*$VDSG<before-completing-the-stack-and-heap-definitions> */
|
|
dxe_block0_stack_and_heap_expand NO_INIT BW
|
{
|
INPUT_SECTION_ALIGN(4)
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RESERVE_EXPAND(heaps_and_system_stack_in_L1, heaps_and_system_stack_in_L1_length, 0, 8)
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ldf_stack_space = heaps_and_system_stack_in_L1;
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ldf_stack_end = (ldf_stack_space + (((heaps_and_system_stack_in_L1_length * 57344) / 189440) - 8));
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ldf_stack_length = ldf_stack_end - ldf_stack_space;
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L1Mem_space = ldf_stack_end + 8;
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L1Mem_end = (L1Mem_space + (((heaps_and_system_stack_in_L1_length * 132096) / 189440) - 8));
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L1Mem_length = L1Mem_end - L1Mem_space;
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} > mem_block0_bw
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dxe_l2_stack_and_heap_expand NO_INIT BW
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{
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INPUT_SECTION_ALIGN(4)
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/*$VDSG<insert-input-sections-at-the-start-of-dxe_L2_stack_and_heap> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-input-sections-at-the-start-of-dxe_L2_stack_and_heap> */
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RESERVE_EXPAND(heaps_and_system_stack_in_L2, heaps_and_system_stack_in_L2_length, 0, 8)
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ldf_heap_space = heaps_and_system_stack_in_L2;
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ldf_heap_end = (ldf_heap_space + (heaps_and_system_stack_in_L2_length - 8));
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ldf_heap_length = ldf_heap_end - ldf_heap_space;
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} > MY_L2_CACHED_MEM
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dxe_sdram_stack_and_heap_expand NO_INIT BW
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{
|
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/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_stack_and_heap> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-input-sections-at-the-start-of-dxe_sdram_stack_and_heap> */
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RESERVE_EXPAND(heaps_and_system_stack_in_L3, heaps_and_system_stack_in_L3_length, 0, 8)
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DDRHeap_space = heaps_and_system_stack_in_L3 + 8;
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DDRHeap_end = (DDRHeap_space + (heaps_and_system_stack_in_L3_length - 8));
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DDRHeap_length = DDRHeap_end - DDRHeap_space;
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} > SDRAM_STACK_HEAP_BLOCK
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// ------------------------------------------------------------------
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|
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/*$VDSG<insert-new-sections-at-the-end> */
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/* Text inserted between these $VDSG comments will be preserved */
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/*$VDSG<insert-new-sections-at-the-end> */
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} /* SECTIONS */
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} /* 21569_CORE0_SHARC0 */
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