/*
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* dma.c
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*
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* Created on: 2022Äê1ÔÂ7ÈÕ
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* Author: graydon
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*/
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#include <stdint.h>
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#include <services/int/adi_sec.h>
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#include <services/int/adi_int.h>
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#include <signal.h>
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#include "dma.h"
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#include "linkport.h"
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struct DMARegs
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{
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volatile void* dscptr_next;
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volatile uint32_t addrstart;
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volatile uint32_t cfg;
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volatile uint32_t xcnt;
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volatile uint32_t xmod;
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volatile uint32_t ycnt;
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volatile uint32_t ymod;
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volatile void* dscptr_cur;
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volatile void* dscptr_prv;
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volatile uint32_t addr_cur;
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volatile uint32_t stat;
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volatile uint32_t xcnt_cur;
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volatile uint32_t ycnt_cur;
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volatile uint32_t bwlcnt;
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volatile uint32_t bwlcnt_cur;
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volatile uint32_t bwmcnt;
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volatile uint32_t bwmcnt_cur;
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};
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#define MSIZE 2
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#define PSIZE 2
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#define DMACONFIG ((PSIZE<<4)|(MSIZE<<8)|(1<<20))
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static volatile DMARegsDef* gDMARegs[] = {
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DMA0,DMA1,DMA2,DMA3,DMA4,DMA5,DMA6,DMA7,
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DMA10,DMA11,DMA12,DMA13,DMA14,DMA15,DMA16,DMA17,
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DMA30,DMA36
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};
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static uint32_t iid[] = {
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INTR_SPORT0_A_DMA,INTR_SPORT0_B_DMA,INTR_SPORT1_A_DMA,INTR_SPORT1_B_DMA,
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INTR_SPORT2_A_DMA,INTR_SPORT2_B_DMA,INTR_SPORT3_A_DMA,INTR_SPORT3_B_DMA,
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INTR_SPORT4_A_DMA,INTR_SPORT4_B_DMA,INTR_SPORT5_A_DMA,INTR_SPORT5_B_DMA,
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INTR_SPORT6_A_DMA,INTR_SPORT6_B_DMA,INTR_SPORT7_A_DMA,INTR_SPORT7_B_DMA,
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INTR_LP0_DMA,INTR_LP1_DMA
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};
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volatile DMARegsDef* get_dma_regs(uint32_t id)
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{
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if(id < sizeof(gDMARegs)/sizeof(DMARegsDef*)) {
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return gDMARegs[id];
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}
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return 0;
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}
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static uvoid DMACallBack (u32 int_id, uvoidptr arg)
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{
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// extern u32 master_intr;
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// extern ubool LinkPortStart;
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// disable_interrupts();
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switch(int_id) {
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case INTR_SPORT0_A_DMA:
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*pREG_DMA0_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT0_B_DMA:
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*pREG_DMA1_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT1_A_DMA:
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*pREG_DMA2_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT1_B_DMA:
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*pREG_DMA3_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT2_A_DMA:
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*pREG_DMA4_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT2_B_DMA:
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*pREG_DMA5_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT3_A_DMA:
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*pREG_DMA6_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT3_B_DMA:
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*pREG_DMA7_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT4_A_DMA:
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*pREG_DMA10_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT4_B_DMA:
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*pREG_DMA11_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT5_A_DMA:
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*pREG_DMA12_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT5_B_DMA:
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*pREG_DMA13_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT6_A_DMA:
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*pREG_DMA14_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT6_B_DMA:
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*pREG_DMA15_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT7_A_DMA:
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*pREG_DMA16_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_SPORT7_B_DMA:
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*pREG_DMA17_STAT|=BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_LP0_DMA:
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*pREG_DMA30_STAT|= BITM_DMA_STAT_IRQDONE;
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break;
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case INTR_LP1_DMA:
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*pREG_DMA36_STAT|= BITM_DMA_STAT_IRQDONE;
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break;
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}
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AudioProcCallBack(int_id);
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//ÐèÒªµÈ´ý½ÓÊÕ·½×¼±¸ºÃ£¬·ñÔò»á³ö´í...
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// if(LinkPortStart && master_intr == int_id) {
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// LP_transmit();//config output .
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// }
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//adi_int_ClearPending(iid);
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// enable_interrupts();
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}
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void dma_install_interrupt(uint32_t id)
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{
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if(id < sizeof(iid)/sizeof(uint32_t)) {
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adi_sec_SetPriority(iid[id], 48);
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adi_int_InstallHandler(iid[id], DMACallBack, 0, true);
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}
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}
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void dma_config(volatile DMARegsDef* regs, uint32_t desc_address, uint32_t cnt, ubool rx, ubool stop_mode)
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{
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u32 cfg = 0;
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regs->cfg = 0;
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regs->xcnt = cnt;
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regs->xmod = 4;
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if(stop_mode) {
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cfg = (0<<12)|(0<<16)|DMACONFIG; // stop Flow Mode
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regs->addrstart = desc_address;
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}
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else {
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cfg = (4<<12)|(1<<16)|DMACONFIG; //Descriptor List Mode
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regs->dscptr_next = (void*)desc_address;
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}
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if(rx) {
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regs->cfg = cfg | (1<<1) ;
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}
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else {
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regs->cfg = cfg ;
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}
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}
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void dma_enable(volatile DMARegsDef* regs)
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{
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regs->cfg |= 1 ;
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}
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