#include <def21489.h>
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.section/pm seg_pmco; // the kernel must reside in a single input_section
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.global _initPLL_SDRAM2;
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//============================== USER_INIT ===================================
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// This space is provided for the user to insert code. This is only required
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// when a system requires a custom configuration for the DSP.
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// These External Port and PLL settings are for the ADSP-21469 EZkit.
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// Update the settings below to match the requirements for the target board.
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//------------------------------------------------------------------------------
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_initPLL_SDRAM2:
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// Set INDIV bit in PMCTL register
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USTAT1 = dm(PMCTL);
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bit set USTAT1 INDIV;
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dm(PMCTL) = USTAT1;
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// Program PLL multiplier to same value as CLK_CFGx pins/previously programmed value in software
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dm(PMCTL) = USTAT1;
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// Place PLL in bypass mode
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bit set USTAT1 PLLBP;
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dm(PMCTL) = USTAT1;
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// Wait recommended number of cycles
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lcntr=4096, do loopwait1 until lce;
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loopwait1:
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nop;
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// Bring PLL out of bypass mode by clearing PLLBP bit
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bit clr USTAT1 PLLBP;
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dm(PMCTL) = USTAT1;
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// Wait for PLL bypass exit
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lcntr=16, do loopwait2 until lce;
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loopwait2:
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nop;
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USTAT1 = dm(PMCTL);
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// Clear the previous PLL multiplier
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bit clr USTAT1 PLLM63;
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// Clear the INDIV bit
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bit clr USTAT1 INDIV;
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// or set the INDIV bit
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// bit set USTAT1 INDIV;
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dm(PMCTL) = USTAT1;
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// Set PMCTL with the desired values
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// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
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// Fcclk = (CLKIN * 2 * M) / (N * D)
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// VCO frequency = 2*fINPUT*PLLM = 2*25*16 = 800 <= fVCOmax (800 MHz)
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// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1
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// Core clock = (25 MHz * 2* 16) /(2 * 1) = 400 MHz
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// SDRAM clock = 400 / 2.5 = 160 MHz.
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ustat3 = PLLM16|PLLD2|SDCKR2_5|DIVEN;
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dm(PMCTL) = ustat3;
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bit set ustat3 PLLBP; //Setting the PLLBP bit
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bit clr ustat3 DIVEN; //Clearing the DIVEN bit
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dm(PMCTL) = ustat3; //Putting the PLL into bypass mode
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// Wait for at least 4096 cycles for the pll to lock
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lcntr = 5000, do loopend2 until lce;
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loopend2: nop;
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ustat3 = dm(PMCTL);
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bit clr ustat3 PLLBP; //Bringing the PLL out of bypass mode
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dm(PMCTL) = ustat3;
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lcntr=16, do again until lce; //Wait for around 15 CCLK cycles for output dividers to stabilize
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again: nop;
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ustat1 = dm(PMCTL1);
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bit set ustat1 FFTACCSEL;
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dm(PMCTL1) = ustat1;
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nop;
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nop;
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nop;
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nop;
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_initPLL_SDRAM2.end:
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//==============================================================================/
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