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#include "global.h"
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#include <sru.h>
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asm("#include <def21489.h>");
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void clearDAIpins(void)
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{
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//------------------------------------------------------------------------
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// Tie the pin buffer inputs LOW for all DAI pins. Even though
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// these pins are inputs to the SHARC, tying unused pin buffer inputs
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// LOW is "good coding style" to eliminate the possibility of
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// termination artifacts internal to the IC. Note that signal
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// integrity is degraded only with a few specific SRU combinations.
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// In practice, this occurs VERY rarely, and these connections are
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// typically unnecessary. This is GROUP D
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SRU(LOW, DAI_PB01_I);
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SRU(LOW, DAI_PB02_I);
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SRU(LOW, DAI_PB03_I);
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SRU(LOW, DAI_PB04_I);
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SRU(LOW, DAI_PB05_I);
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SRU(LOW, DAI_PB06_I);
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SRU(LOW, DAI_PB07_I);
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SRU(LOW, DAI_PB08_I);
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SRU(LOW, DAI_PB09_I);
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SRU(LOW, DAI_PB10_I);
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SRU(LOW, DAI_PB11_I);
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SRU(LOW, DAI_PB12_I);
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SRU(LOW, DAI_PB13_I);
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SRU(LOW, DAI_PB14_I);
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SRU(LOW, DAI_PB15_I);
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SRU(LOW, DAI_PB16_I);
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SRU(LOW, DAI_PB17_I);
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SRU(LOW, DAI_PB18_I);
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SRU(LOW, DAI_PB19_I);
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SRU(LOW, DAI_PB20_I);
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//------------------------------------------------------------------------
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// Tie the pin buffer enable inputs LOW for all DAI pins so
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// that they are always input pins. This is GROUP F.
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SRU(LOW, PBEN01_I);
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SRU(LOW, PBEN02_I);
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SRU(LOW, PBEN03_I);
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SRU(LOW, PBEN04_I);
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SRU(LOW, PBEN05_I);
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SRU(LOW, PBEN06_I);
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SRU(LOW, PBEN07_I);
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SRU(LOW, PBEN08_I);
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SRU(LOW, PBEN09_I);
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SRU(LOW, PBEN10_I);
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SRU(LOW, PBEN11_I);
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SRU(LOW, PBEN12_I);
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SRU(LOW, PBEN13_I);
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SRU(LOW, PBEN14_I);
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SRU(LOW, PBEN15_I);
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SRU(LOW, PBEN16_I);
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SRU(LOW, PBEN17_I);
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SRU(LOW, PBEN18_I);
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SRU(LOW, PBEN19_I);
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SRU(LOW, PBEN20_I);
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}
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void InitDAI()
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{
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clearDAIpins();
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#if defined(DSP818V2)
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SRU(DAI_PB15_O, SPORT1_CLK_I); // DAIP7 (ABCLK) to SPORT1 CLK (RCLK)
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SRU(DAI_PB15_O, SPORT0_CLK_I); // DAIP7 (ABCLK) to SPORT0 CLK (TCLK)
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SRU(DAI_PB15_O, SPORT2_CLK_I); // DAIP7 (ABCLK) to SPORT2 CLK (TCLK)
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SRU(DAI_PB15_O, SPORT3_CLK_I); // DAIP7 (ABCLK) to SPORT2 CLK (TCLK)
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SRU(DAI_PB16_O, SPORT1_FS_I); // DAIP8 (ALRCLK) to SPORT1 FS (RFS1)
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SRU(DAI_PB16_O, SPORT0_FS_I); // DAIP8 (ALRCLK) to SPORT0 FS (TFS0)
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SRU(DAI_PB16_O, SPORT2_FS_I); // DAIP8 (ALRCLK) to SPORT2 FS (TFS2)
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SRU(DAI_PB16_O, SPORT3_FS_I); // DAIP8 (ALRCLK) to SPORT2 FS (TFS2)
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//For Dante CLK
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SRU(DAI_PB15_O, SPORT4_CLK_I);
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SRU(DAI_PB15_O, SPORT5_CLK_I);
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SRU(DAI_PB15_O, SPORT6_CLK_I);
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SRU(DAI_PB15_O, SPORT7_CLK_I);
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//FOR Dante FS
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SRU(DAI_PB16_O, SPORT4_FS_I);
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SRU(DAI_PB16_O, SPORT5_FS_I);
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SRU(DAI_PB16_O, SPORT6_FS_I);
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SRU(DAI_PB16_O, SPORT7_FS_I);
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//FOR Dante RX
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SRU(DAI_PB17_O, SPORT5_DA_I);
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SRU(DAI_PB18_O, SPORT5_DB_I);
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SRU(DAI_PB14_O, SPORT7_DA_I);
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SRU(DAI_PB20_O, SPORT7_DB_I);
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//FOR Dante TX
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SRU(HIGH, PBEN13_I);
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SRU(SPORT4_DA_O, DAI_PB13_I); // DAIP12 (DSDATA1) to SPORT0 DA (TX)
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SRU(HIGH, PBEN19_I);
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SRU(SPORT4_DB_O, DAI_PB19_I); // DAIP11 (DSDATA2) to SPORT0 DB (TX)
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SRU(HIGH, PBEN01_I);
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SRU(SPORT6_DA_O, DAI_PB01_I); // DAIP10 (DSDATA3) to SPORT2 DA (TX)
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SRU(HIGH, PBEN02_I);
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SRU(SPORT6_DB_O, DAI_PB02_I); // DAIP09 (DSDATA4) to SPORT2 DB (TX)
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#else
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SRU(DAI_PB07_O, SPORT1_CLK_I); // DAIP7 (ABCLK) to SPORT1 CLK (RCLK)
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SRU(DAI_PB07_O, SPORT0_CLK_I); // DAIP7 (ABCLK) to SPORT0 CLK (TCLK)
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SRU(DAI_PB07_O, SPORT2_CLK_I); // DAIP7 (ABCLK) to SPORT2 CLK (TCLK)
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SRU(DAI_PB07_O, SPORT3_CLK_I); // DAIP7 (ABCLK) to SPORT2 CLK (TCLK)
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SRU(DAI_PB08_O, SPORT1_FS_I); // DAIP8 (ALRCLK) to SPORT1 FS (RFS1)
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SRU(DAI_PB08_O, SPORT0_FS_I); // DAIP8 (ALRCLK) to SPORT0 FS (TFS0)
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SRU(DAI_PB08_O, SPORT2_FS_I); // DAIP8 (ALRCLK) to SPORT2 FS (TFS2)
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SRU(DAI_PB08_O, SPORT3_FS_I); // DAIP8 (ALRCLK) to SPORT2 FS (TFS2)
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#endif
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SRU(DAI_PB05_O, SPORT1_DA_I); // DAIP5 (ASDATA1) to SPORT1 DA (RX1A)
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SRU(DAI_PB06_O, SPORT1_DB_I); // DAIP6 (ASDATA2) to SPORT1 DB (RX1B)
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SRU(DAI_PB03_O, SPORT3_DA_I); // DAIP5 (ASDATA1) to SPORT1 DA (RX1A)
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SRU(DAI_PB04_O, SPORT3_DB_I); // DAIP6 (ASDATA2) to SPORT1 DB (RX1B)
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SRU(HIGH, PBEN12_I);
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SRU(SPORT0_DA_O, DAI_PB12_I); // DAIP12 (DSDATA1) to SPORT0 DA (TX)
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SRU(HIGH, PBEN11_I);
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SRU(SPORT0_DB_O, DAI_PB11_I); // DAIP11 (DSDATA2) to SPORT0 DB (TX)
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SRU(HIGH, PBEN10_I);
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SRU(SPORT2_DA_O, DAI_PB10_I); // DAIP10 (DSDATA3) to SPORT2 DA (TX)
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SRU(HIGH, PBEN09_I);
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SRU(SPORT2_DB_O, DAI_PB09_I); // DAIP09 (DSDATA4) to SPORT2 DB (TX)
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#ifdef DEMO_BOARD
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//--------------------------------------------------------------------------
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// Route SPI signals to AD1939 Control Port.
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SRU(SPI_MOSI_O, DPI_PB01_I); //Connect MOSI to DPI PB1.
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SRU(DPI_PB02_O, SPI_MISO_I); //Connect DPI PB2 to MISO.
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SRU(SPI_CLK_O, DPI_PB03_I); //Connect SPI CLK to DPI PB3.
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SRU(SPI_FLG0_O, DPI_PB04_I); //Connect SPI FLAG0 to DPI PB4.
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SRU(SPI_MOSI_PBEN_O, DPI_PBEN01_I);
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SRU(SPI_MISO_PBEN_O, DPI_PBEN02_I);
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SRU(SPI_CLK_PBEN_O, DPI_PBEN03_I);
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SRU(SPI_FLG0_PBEN_O, DPI_PBEN04_I);
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#elif defined(DSP818V1)
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SRU(DAI_PB13_O,PCG_EXTA_I);
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SRU(HIGH, PBEN07_I);
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SRU(PCG_CLKA_O,DAI_PB07_I);
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SRU(HIGH, PBEN08_I);
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SRU(PCG_FSA_O,DAI_PB08_I);
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#elif defined(DSP818V2) && !defined(HAS_DANTE)
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//route PCG
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SRU(HIGH, PBEN08_I);
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SRU(DAI_PB07_O,DAI_PB08_I);
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SRU(DAI_PB07_O,PCG_EXTA_I);
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SRU(HIGH, PBEN15_I);
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SRU(PCG_CLKA_O,DAI_PB15_I);
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SRU(HIGH, PBEN16_I);
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SRU(PCG_FSA_O,DAI_PB16_I);
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#endif
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//spiB route.
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SRU (LOW, DPI_PBEN07_I);
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SRU (HIGH, DPI_PBEN08_I);
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SRU (LOW, DPI_PBEN09_I);
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SRU (LOW, DPI_PBEN10_I);
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// SRU(SPIB_MOSI_PBEN_O, DPI_PBEN07_I);
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// SRU(SPIB_MISO_PBEN_O, DPI_PBEN08_I);
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// SRU(SPIB_CLK_PBEN_O, DPI_PBEN09_I);
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// SRU(SPIB_FLG0_PBEN_O, DPI_PBEN10_I);
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SRU(DPI_PB07_O,SPIB_MOSI_I);
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SRU(SPIB_MISO_O,DPI_PB08_I); //Connect DPI PB2 to MISO.
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SRU(DPI_PB09_O,SPIB_CLK_I); //Connect SPI CLK to DPI PB3.
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SRU(DPI_PB10_O,SPIB_DS_I);
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}
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