#include <def21489.h>
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.global _InitPLL;
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.global _InitSDRAM;
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.global _InitAMI;
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.section/pm seg_pmco;
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_InitPLL:
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// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
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// Fcclk = (CLKIN * 2 * M) / (N * D)
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// VCO max frequency = 800 GHz
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// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1
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// Core clock = (25MHz * 2* 16) /(2 * 1) = 400 MHz
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// SDRAM clock = 400 / 2.5 = 160 MHz.
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ustat3 = PLLM16|PLLD2|SDCKR2_5;
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changePLL:
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bit set ustat3 DIVEN;
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dm(PMCTL) = ustat3;
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bit set ustat3 PLLBP; //Place the PLL in bypass mode.
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bit clr ustat3 DIVEN; //Clear the DIVEN bit while placing the PLL in bypass mode.
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dm(PMCTL) = ustat3;
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// Wait for at least 4096 cycles for the pll to lock
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lcntr = 5000, do loopend2 until lce;
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loopend2: nop;
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ustat3 = dm(PMCTL); //Reading the PMCTL register will return the DIVEN bit value as zero.
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bit clr ustat3 PLLBP; //Take the PLL out of bypass mode.
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dm(PMCTL) = ustat3;
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lcntr = 16, do loopend3 until lce;
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loopend3: nop;
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_InitPLL.end: rts;
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_InitSDRAM:
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// SDRAM memory on EZ-KIT - MT48LC16M16A2-6A
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//5.4ns @ CL = 3 ,167 MHz speed
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// Parameters
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// Config - 64M x 16(16M x 16 x 4)
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// Speed - 167 MHz
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// CAS Latency - 3
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// Row addressing - 8K(A0-A12)
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// Column addressing - 512(A0-A8)
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// No of Banks - 4
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//tRAS - 42ns
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//tRCD - 18ns
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//tRP - 18ns
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//tRC - 60ns( tRP + tRAS >= tRC)
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//tWR - (1CLK + 6ns)/12
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//For the 160 MHz case, tSDCLK = 1/160 MHz = 6.25ns
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// CAS Latency = 3
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// tRCD = 18 / 6.25 = 3(2.88)
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// tRP = 18 / 6.25 = 3(2.88)
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// tRC = 60 / 6.25 = 10(9.6)
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// tRAS = 42/ 6.25 = 7(6.72)
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// tWR = (6.25 + 6)/ 12 = 2(1.02)
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// fSDCLK = 160 MHz
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// tREF= 64ms
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// NRA = 8192
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// RDIV = ((f SDCLK X t REF)/NRA) - (t RAS + t RP)
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// RDIV = (((160 X 10^6 x 64 x 10^-3)/8192) - (7 + 3))
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// RDIV = 1240 = 0x4D8
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#define RDIV (0x4D8)
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ustat1 = dm(SYSCTL);
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bit set ustat1 MSEN;
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dm(SYSCTL) = ustat1;
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// Mapping Bank 0 to SDRAM
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ustat1 = dm(EPCTL);
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bit set ustat1 B0SD;
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bit clr ustat1 B1SD|B2SD|B3SD;
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dm(EPCTL) = ustat1;
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ustat1 = RDIV;
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bit set ustat1 SDROPT | BIT_17; // Enabling SDRAM read optimization
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// Setting the Modify to 1
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dm(SDRRC) = ustat1;
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// Programming SDRAM control register
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ustat1 = 0;
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bit set ustat1 SDCL3|SDTRAS7|SDTRP3|SDCAW9|SDPSS|SDTWR2|SDTRCD3|SDRAW13|X16DE;
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dm(SDCTL) = ustat1;
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r0 = dm(0x200000);
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nop;
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nop;
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nop;
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nop;
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_InitSDRAM.end: rts;
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_InitAMI:
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ustat1 = dm(SYSCTL);
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bit set ustat1 EPDATA32;
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dm(SYSCTL) = ustat1;
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// Flash is connected on Bank 1
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// Programming maximum waitstates
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ustat1 = AMIEN | BW8 | WS31 ;
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dm(AMICTL1) = ustat1;
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// SRAM is connected on Bank 2
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// SRAM part used - IS61WV102416BLL
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// As per datasheet access time is 10 ns, 8ns
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// Programming waitstates = 2
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ustat1 = AMIEN | BW16 | WS2 ;
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dm(AMICTL3) = ustat1;
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_InitAMI.end: rts;
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