/*
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** ADSP-1802 linker description file generated on Aug 05, 2024 at 15:33:23.
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*/
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/*
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** Copyright (C) 2000-2024 Analog Devices Inc., All Rights Reserved.
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**
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** This file is generated automatically based upon the options selected
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** in the System Configuration utility. Changes to the LDF configuration
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** should be made by modifying the appropriate options rather than editing
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** this file. To access the System Configuration utility, double-click the
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** system.svc file from a navigation view.
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**
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** Custom additions can be inserted within the user-modifiable sections. These
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** sections are bounded by comments that start with "$VDSG". Only changes
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** placed within these sections are preserved when this file is re-generated.
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**
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** Product : CrossCore Embedded Studio
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** Tool Version : 6.2.3.6
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*/
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ARCHITECTURE(ADSP-1802)
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/*
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** Define a linked library list.
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*/
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$LIBRARIES =
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libcc.dlb
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,libc.dlb
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,libio.dlb
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,libcpp.dlb
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,libosal_noos.dlb
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,libprofile.dlb
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,libssl.dlb
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,libdsp.dlb
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,libdyn.dlb
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;
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/*
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** Define a linked objects list.
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*/
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$OBJECTS =
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"app_startup.doj"
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,$COMMAND_LINE_OBJECTS
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;
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/*
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** List of all objects and libraries.
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*/
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$OBJS_LIBS = $OBJECTS, $LIBRARIES;
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/*
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** List of objects and libraries which prefer internal memory as
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** specified by prefersMem attribute.
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*/
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$OBJS_LIBS_INTERNAL =
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$OBJS_LIBS{prefersMem("internal")}
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;
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/*
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** List of objects and libraries which don't have a preference for
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** external memory as specified by prefersMem attribute.
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*/
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$OBJS_LIBS_NOT_EXTERNAL =
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$OBJS_LIBS{!prefersMem("external")}
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;
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MEMORY
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{
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/* ADSP-1802 MEMORY MAP.
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**
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** The SHARC 1802 has 5Mbit RAM in total.
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**
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** -------------------------- BLOCK 0 ---------------------------------------
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** 0x0008 C000 to 0x0009 3FFF Normal word (48) Space (1.5 Mbit RAM)
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** 0x0009 2000 to 0x0009 DFFF Normal word (32) Space (1.5 Mbit RAM)
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** 0x0012 4000 to 0x0013 BFFF Short word (16) Space (1.5 Mbit RAM)
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**
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** Notes:
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** 1) The interrupt Vector Table (IVT) code is placed in internal memory
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** by default and has to use ISA (NW, 48 bit) instructions.
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** 2) The loader kernel uses 256 ISA instructions from the start of the
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** IVT. The final action it does is to load the application code to these
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** address overwriting it's own code. The application code in these
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** addresses therefore must also be ISA instructions. Do not put
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** VISA (SW) instructions in these 256 locations.
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*/
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mem_iv_code { TYPE(PM RAM) START(0x0008C000) END(0x0008C0A7) WIDTH(48) }
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mem_block0_nwco { TYPE(PM RAM) START(0x0008C0A8) END(0x0008C0FF) WIDTH(48) }
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mem_block0_sw16 { TYPE(SW RAM) START(0x00124300) END(0x0013BFFF) WIDTH(16) }
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/*
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** -------------------------- BLOCK 1 ---------------------------------------
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** 0x000A C000 to 0x000B 3FFF Normal word (48) Space (1.5 Mbit RAM)
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** 0x000B 2000 to 0x000B DFFF Normal word (32) Space (1.5 Mbit RAM)
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** 0x0016 4000 to 0x0017 BFFF Short word (16) Space (1.5 Mbit RAM)
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*/
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mem_block1_dm32 { TYPE(DM RAM) START(0x000B2000) END(0x000B7FFF) WIDTH(32) }
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mem_internal1 { TYPE(DM RAM) START(0x000B8000) END(0x000BDFFF) WIDTH(32) }
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/*
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** -------------------------- BLOCK 2 ---------------------------------------
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** 0x000C 0000 to 0x000C 5554 Normal word (48) Space (1 Mbit RAM)
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** 0x000C 0000 to 0x000C 7FFF Normal word (32) Space (1 Mbit RAM)
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** 0x0018 0000 to 0x0018 FFFF Short word (16) Space (1 Mbit RAM)
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*/
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mem_block2_pm32 { TYPE(PM RAM) START(0x000C0000) END(0x000C1FFF) WIDTH(32) }
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mem_internal2 { TYPE(PM RAM) START(0x000C2000) END(0x000C7FFF) WIDTH(32) }
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/*
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** -------------------------- BLOCK 3 ---------------------------------------
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** 0x000E 0000 to 0x000E 5554 Normal word (48) Space (1 Mbit RAM)
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** 0x000E 0000 to 0x000E 7FFF Normal word (32) Space (1 Mbit RAM)
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** 0x001C 0000 to 0x001C FFFF Short word (16) Space (1 Mbit RAM)
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*/
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mem_block3_dm32 { TYPE(DM RAM) START(0x000E0000) END(0x000E7FFF) WIDTH(32) }
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/*
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** -------------------------- L2 Memory -------------------------------------
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** There is 1MB of L2 memory split over two banks.
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**
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** This LDF defines L2 memory bank 0 section only in SW format. It is
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** not necessary to partition memory for different widths and different
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** input types.
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**
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** The output sections that populate the L2 bank 0 memory are defined to
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** use one of the following qualifiers:
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**
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** PM (ISA code)
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** PM 32 (PM data)
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** DM (DM data)
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** SW (VISA code)
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**
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** The linker filters the inputs for each output section to match
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** these output section qualfiers. Each output section uses the same
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** SW memory segment which the linker packs correctly for each
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** qualifier.
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**
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*/
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mem_l2bank0_sw16 { TYPE(SW RAM) START(0x0060000A) END(0x00639FFF) WIDTH(16) }
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mem_scene_data { TYPE(SW RAM) START(0x0063A000) END(0x0063FFFF) WIDTH(16) }
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/* L2 Bank 1 is only for data so is defined in DM format. */
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mem_l2bank1_dm32 { TYPE(DM RAM) START(0x04000000) END(0x0401FFFF) WIDTH(32) }
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} /* MEMORY */
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PROCESSOR p0
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{
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OUTPUT($COMMAND_LINE_OUTPUT_FILE)
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KEEP(_main)
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KEEP(___ctor_NULL_marker)
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SECTIONS
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{
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#define IV_CODE dxe_iv_code
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IV_CODE PM
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{
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INPUT_SECTIONS( $OBJECTS(iv_code) )
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} > mem_iv_code
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dxe_block0_nw_code PM
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{
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_code seg_init seg_pmco) )
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} > mem_block0_nwco
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dxe_block0_sw_code_prio0 SW
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{
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FILL(0x1) /* fill in gaps in the memory with NOPs */
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_code_sw seg_int_code) )
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} > mem_block0_sw16
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dxe_block0_nw_code_prio0 PM
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{
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_code) )
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INPUT_SECTIONS( $OBJS_LIBS(seg_init) )
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} > mem_block0_sw16
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dxe_block0_sw_code_prio1 SW
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{
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FILL(0x1) /* fill in gaps in the memory with NOPs */
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_swco seg_pmco) )
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} > mem_block0_sw16
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dxe_block0_nw_code_prio1 PM
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL( seg_pmco ) )
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} > mem_block0_sw16
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dxe_block0_sw_code_prio2 SW
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{
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FILL(0x1) /* fill in gaps in the memory with NOPs */
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_swco seg_pmco) )
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INPUT_SECTIONS( $OBJS_LIBS(seg_swco seg_pmco) )
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} > mem_block0_sw16
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#define BLOCK0_SW_CODE dxe_block0_sw_code_prio3
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BLOCK0_SW_CODE SW
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{
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FILL(0x1) /* fill in gaps in the memory with NOPs */
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INPUT_SECTIONS( $OBJS_LIBS(seg_swco seg_pmco) )
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} > mem_block0_sw16
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#define BLOCK0_NW_CODE dxe_block0_nw_code_prio3
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BLOCK0_NW_CODE PM
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{
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INPUT_SECTIONS( $OBJS_LIBS(seg_pmco) )
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} > mem_block0_sw16
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dxe_block2_pm_data
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_pmda) )
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_pmda) )
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INPUT_SECTIONS( $OBJS_LIBS(seg_pmda) )
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} > mem_block2_pm32
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dxe_block1_dm_data_prio0
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{
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RESERVE(heaps_and_system_stack_in_L1, heaps_and_system_stack_in_L1_length = 12288, 2)
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_data) )
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} > mem_block1_dm32
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dxe_block1_dm_data_prio1
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda seg_vtbl) )
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} > mem_block1_dm32
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dxe_block1_bsz_prio1 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(.bss) )
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} > mem_block1_dm32
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dxe_block1_dm_data_prio2
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{
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda seg_vtbl) )
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} > mem_block1_dm32
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dxe_block1_bsz_prio2 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(.bss) )
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} > mem_block1_dm32
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dxe_block1_dm_data_prio3
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{
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INPUT_SECTIONS( $OBJS_LIBS(seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_block1_dm32
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dxe_block1_bsz_prio3 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS(.bss) )
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} > mem_block1_dm32
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dxe_block3_dm_data_prio0
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{
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RESERVE(heaps_and_system_heap_in_L1, heaps_and_system_heap_in_L1_length = 12288, 2)
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_data) )
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} > mem_block3_dm32
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dxe_block3_dm_data_prio1
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(seg_dmda seg_vtbl) )
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} > mem_block3_dm32
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dxe_block3_bsz_prio1 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS_INTERNAL(.bss) )
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} > mem_block3_dm32
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dxe_block3_dm_data_prio2
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{
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(seg_dmda seg_vtbl) )
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} > mem_block3_dm32
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dxe_block3_bsz_prio2 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(.bss) )
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} > mem_block3_dm32
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dxe_block3_dm_data_prio3
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{
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INPUT_SECTIONS( $OBJS_LIBS(seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_block3_dm32
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dxe_block3_bsz_prio3 ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS(.bss) )
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} > mem_block3_dm32
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dxe_block3_overflow_data
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{
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/* Use any unused memory in the dm data designated blocks 1 and 3
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** for pm data if we've not been able to map it to block 2.
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*/
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INPUT_SECTIONS( $OBJS_LIBS(seg_pmda) )
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} > mem_block3_dm32
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dxe_block3_heap NO_INIT
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{
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RESERVE_EXPAND(heaps_and_system_heap_in_L1, heaps_and_system_heap_in_L1_length, 0, 2)
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ldf_heap_space = heaps_and_system_heap_in_L1;
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ldf_heap_end = (ldf_heap_space + (heaps_and_system_heap_in_L1_length - 2)) & 0xfffffffe;
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ldf_heap_length = ldf_heap_end - ldf_heap_space;
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} > mem_block3_dm32
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dxe_block1_overflow_data
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{
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/* Use any unused memory in the dm data designated blocks 1 and 3
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** for pm data if we've not been able to map it to block 2.
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*/
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INPUT_SECTIONS( $OBJS_LIBS(seg_pmda) )
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} > mem_block1_dm32
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dxe_block1_stack NO_INIT
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{
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RESERVE_EXPAND(heaps_and_system_stack_in_L1, heaps_and_system_stack_in_L1_length, 0, 2)
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ldf_stack_space = heaps_and_system_stack_in_L1;
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ldf_stack_end = (ldf_stack_space + (heaps_and_system_stack_in_L1_length - 2)) & 0xfffffffe;
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ldf_stack_length = ldf_stack_end - ldf_stack_space;
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} > mem_block1_dm32
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dxe_block2_overflow_data
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{
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// Use any unused memory in the pm data designated block 2 for
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// dm data if we've not been able to map it to the dm data blocks
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// 1 and 3.
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INPUT_SECTIONS( $OBJS_LIBS(seg_int_data seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_block2_pm32
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dxe_block2_bsz ZERO_INIT
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{
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INPUT_SECTIONS( $OBJS_LIBS(.bss) )
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} > mem_block2_pm32
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// ------------------------------------------------------------------
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// L2 - core memory
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dxe_l2bank0_sw_code SW
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{
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FILL(0x1) /* fill in gaps in the memory with NOPs */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_swco seg_swco seg_pmco) )
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} > mem_l2bank0_sw16
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dxe_l2bank0_nw_code PM
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{
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/* ISA code */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_pmco seg_pmco) )
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} > mem_l2bank0_sw16
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dxe_l2bank0_pm_data PM 32
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{
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/* L2 pm data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_pmda) )
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} > mem_l2bank0_sw16
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dxe_l2bank1_cpp_ctors
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{
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FORCE_CONTIGUITY
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__ctors = .; /* __ctors points to the start of the section */
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INPUT_SECTIONS( $OBJS_LIBS(seg_ctdm) )
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INPUT_SECTIONS( $OBJS_LIBS(seg_ctdml) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_cpp_eh_gdt
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{
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FORCE_CONTIGUITY
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/* C++ exceptions data table */
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INPUT_SECTIONS( $OBJS_LIBS(.gdt) )
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INPUT_SECTIONS( $OBJS_LIBS(.gdtl) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_dm_data
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{
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RESERVE(heaps_and_system_stack_in_L2, heaps_and_system_stack_in_L2_length = 130048, 2)
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_dmda seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_bsz ZERO_INIT
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{
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/* L2 zero init data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2_bsz_data seg_bsz_data .bss) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_noinit NO_INIT
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{
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/* L2 no init data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_pm_data
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{
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/* L2 pm data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_pmda) )
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} > mem_l2bank1_dm32
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dxe_l2bank1_heaps_and_stack_expand NO_INIT
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{
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/* Expand the stack/heap to use the rest of available L2 bank 1 */
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RESERVE_EXPAND(heaps_and_system_stack_in_L2, heaps_and_system_stack_in_L2_length, 0, 2)
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MyHeap2_space = heaps_and_system_stack_in_L2 + 2;
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MyHeap2_end = (MyHeap2_space + (heaps_and_system_stack_in_L2_length - 2)) & 0xfffffffe;
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MyHeap2_length = MyHeap2_end - MyHeap2_space;
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} > mem_l2bank1_dm32
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// Place DM data we couldn't link internally or to L2 bank 1 into
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// any remaining memory available in L2 bank 0.
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dxe_l2bank0_dm_data DM
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{
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RESERVE(heaps_and_system_heap_in_L2, heaps_and_system_heap_in_L2_length = 76800, 2)
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2 seg_l2_dmda seg_dmda seg_vtbl .rtti .cht .edt) )
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} > mem_l2bank0_sw16
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seg_scene_data DM
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{
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INPUT_SECTIONS( $OBJECTS(scene_mem) $LIBRARIES(scene_mem))
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} > mem_scene_data
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dxe_l2bank0_bsz ZERO_INIT DM
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{
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/* L2 zero init data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2_bsz_data seg_bsz_data .bss) )
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} > mem_l2bank0_sw16
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dxe_l2bank0_noinit NO_INIT DM
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{
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/* L2 no init data */
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INPUT_SECTIONS( $OBJS_LIBS(seg_l2_noinit_data seg_noinit_data) )
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} > mem_l2bank0_sw16
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dxe_l2bank0_heaps_and_stack_expand NO_INIT
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{
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/* Expand the stack/heap to use the rest of available L2 bank 1 */
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RESERVE_EXPAND(heaps_and_system_heap_in_L2, heaps_and_system_heap_in_L2_length, 0, 2)
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MyHeap4_space = heaps_and_system_heap_in_L2 + 2;
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MyHeap4_end = (MyHeap4_space + (heaps_and_system_heap_in_L2_length - 2)) & 0xfffffffe;
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MyHeap4_length = MyHeap4_end - MyHeap4_space;
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} > mem_l2bank0_sw16
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} /* SECTIONS */
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} /* p0 */
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