/*
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* board.c
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*
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* Created on: 2021Äê9ÔÂ1ÈÕ
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* Author: graydon
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*/
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#include <stdio.h>
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#include <signal.h>
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#include <SRU.h>
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#include <def1802.h>
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#include <cdef1802.h>
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//#include <def21489.h>
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//#include <cdef21489.h>
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#include "board.h"
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#include "config.h"
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#include "sport.h"
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#include "string.h"
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//static ubool has_dante = ufalse;
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void pinmux_config(void)
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{
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int i ,j ;
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//GPIO
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SRU(HIGH, DPI_PBEN11_I); //0-busy,1-idle
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SRU(HIGH, DPI_PBEN12_I); //0-send, 1-recv
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SRU(LOW,DPI_PB12_I);
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SRU(LOW,DPI_PB11_I);
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SRU(HIGH,DPI_PBEN13_I);//led
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SRU(HIGH,DPI_PBEN14_I);
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for(i=0;i<3;i++) {
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SRU(LOW,DPI_PB13_I);
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SRU(LOW,DPI_PB14_I);
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for(j=0 ;j < 2000000 ;j++);
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SRU(HIGH,DPI_PB13_I);
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SRU(HIGH,DPI_PB14_I);
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for(j=0 ;j < 2000000 ;j++);
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}
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}
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void InitPCG(void);
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void InitSRC(void);
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void SportsConfig(void);
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void Audio_Config(void)
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{
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SRU(DAI_PB02_O, SPORT0_CLK_I);
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SRU(DAI_PB02_O, SPORT1_CLK_I);
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SRU(DAI_PB02_O, SPORT2_CLK_I);
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SRU(DAI_PB02_O, SPORT3_CLK_I);
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// SRU(DAI_PB02_O, SPORT4_CLK_I);
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// SRU(DAI_PB02_O, SPORT5_CLK_I);
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// SRU(DAI_PB02_O, SPORT6_CLK_I);
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// SRU(DAI_PB02_O, SPORT7_CLK_I);
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SRU(DAI_PB01_O, SPORT0_FS_I);
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SRU(DAI_PB01_O, SPORT1_FS_I);
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SRU(DAI_PB01_O, SPORT2_FS_I);
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SRU(DAI_PB01_O, SPORT3_FS_I);
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// SRU(DAI_PB01_O, SPORT4_FS_I);
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// SRU(DAI_PB01_O, SPORT5_FS_I);
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// SRU(DAI_PB01_O, SPORT6_FS_I);
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// SRU(DAI_PB01_O, SPORT7_FS_I);
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//analog input
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SRU(DAI_PB17_O, SPORT1_DA_I);
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SRU(DAI_PB14_O, SPORT1_DB_I);
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SRU(DAI_PB08_O, SPORT3_DA_I);
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SRU(DAI_PB10_O, SPORT3_DB_I);
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//analog output
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SRU(HIGH, PBEN18_I); //OUT0
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SRU(SPORT0_DA_O, DAI_PB18_I);
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SRU(HIGH, PBEN04_I); //OUT1
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SRU(SPORT0_DB_O, DAI_PB04_I);
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SRU(HIGH, PBEN20_I); //OUT2
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SRU(SPORT2_DA_O, DAI_PB20_I);
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SRU(HIGH, PBEN09_I); //OUT3
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SRU(SPORT2_DB_O, DAI_PB09_I);
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#if 1
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// SRC ÍâΧʱÖÓ
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SRU(DAI_PB03_O, SRC0_CLK_IP_I);
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SRU(DAI_PB13_O, SRC0_FS_IP_I);
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SRU(DAI_PB03_O, SRC1_CLK_OP_I);
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SRU(DAI_PB13_O, SRC1_FS_OP_I);
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// SRC ÄÚ²¿Ê±ÖÓ
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SRU(DAI_PB02_O, SPORT4_CLK_I);
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SRU(DAI_PB02_O, SPORT5_CLK_I);
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SRU(DAI_PB01_O, SPORT4_FS_I);
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SRU(DAI_PB01_O, SPORT5_FS_I);
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SRU(DAI_PB02_O, SRC0_CLK_OP_I);
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SRU(DAI_PB01_O, SRC0_FS_OP_I);
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SRU(DAI_PB02_O, SRC1_CLK_IP_I);
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SRU(DAI_PB01_O, SRC1_FS_IP_I);
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// DATAÊäÈëASRC
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SRU(DAI_PB07_O, SRC0_DAT_IP_I);
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SRU(SRC0_DAT_OP_O, SPORT5_DA_I);
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// ASRCÊä³öDATA
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SRU(SPORT4_DA_O, SRC1_DAT_IP_I);
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SRU(HIGH, PBEN19_I);
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SRU(SRC1_DAT_OP_O, DAI_PB19_I);
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#else
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SRU(DAI_PB03_O, SPORT4_CLK_I);
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SRU(DAI_PB03_O, SPORT5_CLK_I);
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SRU(DAI_PB13_O, SPORT5_FS_I);
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SRU(DAI_PB13_O, SPORT5_FS_I);
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SRU(DAI_PB19_O, SPORT5_DA_I);
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SRU(HIGH, PBEN07_I);
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SRU(SPORT4_DA_O, DAI_PB07_I);
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#endif
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//CLOCK
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SRU(HIGH, PBEN02_I); //clk
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SRU(HIGH, PBEN01_I); //fs
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SRU(PCG_CLKC_O,DAI_PB02_I);
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SRU(PCG_FSC_O,DAI_PB01_I);
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SRU(DAI_PB06_O,PCG_EXTC_I);
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InitPCG();
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InitSRC();
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SportsConfig();
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}
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void SportsConfig(void)
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{
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#if 1
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int i ;
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struct SportDef sports[8];
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memset(sports , 0, sizeof(struct SportDef)*8);
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for (i = 0 ;i < 6;i ++){
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sports[i].clke = 0;
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sports[i].enable = 1;
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sports[i].enable_sec = 1;
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sports[i].lfs = 0;
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sports[i].mfd = 0;
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sports[i].opmode = 1;
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sports[i].slots = 2;
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sports[i].spid = i;
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sports[i].vld_a = 2;
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sports[i].vld_b = 2;
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sports[i].rx = i&0x1;
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sports[i].interrupt =0 ;
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}
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sports[5].interrupt = 1; //sport 1 interrupt.
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sports[4].enable_sec = 0;
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sports[4].clke = 0;
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sports[4].lfs = 0;
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sports[5].enable_sec = 0;
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sports[5].clke = 0;
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sports[5].lfs = 0;
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for(i = 0; i < 8 ; i++) {
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if(sports[i].enable && sports[i].spid < 8) {
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sport_config(&sports[i]);
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}
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}
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#else
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InitSPORT(0,0);
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#endif
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}
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void InitPCG(void)
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{
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int n,r0 ;
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int fs_div = MCLK/SAMPLE_RATE;
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int sclk_div = MCLK/(SAMPLE_RATE*32*8);
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int sclk_div_48k = MCLK/(SAMPLE_RATE*32*2);
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//TDM
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*pPCG_CTLA1 =0 ; *pPCG_CTLA0 =0;
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for (n=0; n<16; n++)asm("NOP;");
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r0 = sclk_div | CLKASOURCE | FSASOURCE;
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*pPCG_CTLA1 = r0 ;
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r0 = fs_div | ENFSA | ENCLKA;
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*pPCG_CTLA0 = r0;
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//bypass mode PCGB , get invert sclk
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*pPCG_CTLB1 =0 ; *pPCG_CTLB0 =0;
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for (n=0; n<16; n++)asm("NOP;");
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*pPCG_PW1 = 2| INVFSB ;
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r0 = sclk_div | CLKBSOURCE | FSBSOURCE;
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*pPCG_CTLB1 = r0;
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r0 = ENFSB | ENCLKB;
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*pPCG_CTLB0 = r0;
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//IIS
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*pPCG_CTLC1 =0 ; *pPCG_CTLC0 =0;
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for (n=0; n<16; n++)asm("NOP;");
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r0 = sclk_div_48k| CLKCSOURCE | FSCSOURCE | ((sclk_div_48k/2)<<20);
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*pPCG_CTLC1 = r0 ;
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r0 = fs_div | ENFSC | ENCLKC;
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*pPCG_CTLC0 = r0;
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}
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void InitSRC(void)
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{
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//============================================================
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//
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// Configure SRC Control Register (SRCCTL0).
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//
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// SRC1_IN_I2S : SRC1 Serial Input Format= I2S mode
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// SRC1_OUT_I2S: SRC1 Serial Output Format= I2S mode
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// SRC1_OUT_24 : Output Word Length= 24 bits
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//------------------------------------------------------------
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*pSRCCTL0 = SRC0_IN_I2S | SRC0_OUT_I2S | SRC0_OUT_24 | SRC1_IN_I2S | SRC1_OUT_I2S | SRC1_OUT_24;
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// Enable SRC1 in a different cycle than setting the configuration
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*pSRCCTL0 |= SRC0_ENABLE|SRC1_ENABLE;
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// *pSRCCTL1 = SRC2_IN_I2S | SRC2_OUT_I2S | SRC2_OUT_24 | SRC3_IN_I2S | SRC3_OUT_I2S | SRC3_OUT_24;
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// // Enable SRC1 in a different cycle than setting the configuration
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// *pSRCCTL1 |= SRC2_ENABLE|SRC3_ENABLE;
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}
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//void PCGsConfig(struct PCGDef pcgs[4])
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//{
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//#if 0
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// u32 i;
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//
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// volatile u32* pcg_pw[4] = {pPCG_PW1, pPCG_PW1 ,pPCG_PW2 ,pPCG_PW2};
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// volatile u32* pcg_ctlc0[4] = {pPCG_CTLA0, pPCG_CTLB0 ,pPCG_CTLC0 ,pPCG_CTLD0};
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// volatile u32* pcg_ctlc1[4] = {pPCG_CTLA1, pPCG_CTLB1 ,pPCG_CTLC1 ,pPCG_CTLD1};
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//
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// *pPCG_PW1 = 0; *pPCG_PW2 = 0;
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//
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// for(i = 0; i < 4; i++) {
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// if (pcgs[i].enable ) {
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// s32 n,r0 ;
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//
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// *pcg_ctlc1[i] =0 ; *pcg_ctlc0[i] =0;
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// for (n=0; n<16; n++)asm("NOP;");
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//
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// if(pcgs[i].opmode) {
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// if(pcgs[i].fs_div > 0) {
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// *pcg_pw[i] |= (i&0x1)?(pcgs[i].width<<16):pcgs[i].width;
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// }
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// else if(pcgs[i].invert){
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// //bypass mode.
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// *pcg_pw[i] |= (i&0x1)?(1<<17):(1<<1);
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// }
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//
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// r0 = pcgs[i].sclk_div| (1<<30) | (1<<31) ;
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// }
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// else {
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// r0 = pcgs[i].sclk_div| (1<<30) | (1<<31) | ((pcgs[i].sclk_div/2)<<20);
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// }
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// *pcg_ctlc1[i] = r0 ;
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//
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// r0 = pcgs[i].fs_div | (1<<30) | (1<<31) ;
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// *pcg_ctlc0[i] = r0;
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// }
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// }
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//#else
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// InitPCG();
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//#endif
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//}
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//void SRCsConfig(struct SRCDef src[4])
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//{
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// u32 reg[4] = {0 ,0, 0, 0};
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//
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// for(u32 i = 0 ;i < 4 ;i ++) {
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// if(src[i].enable) {
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// switch (src[i].format) {
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// case 0:
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// break;
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// case 1:
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// //iis
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// reg[i] = (1<<2) | (1<<10) | (1<<15);
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// break;
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// case 2:
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// //tdm
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// reg[i] = (2<<2) | (2<<10) | (1<<15);
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// break;
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// case 3:
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// break;
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// }
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// }
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// }
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// *pSRCCTL0 = reg[0]|(reg[1]<<16);
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// *pSRCCTL1 = reg[2]|(reg[3]<<16);
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//
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//}
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void DAI_config()
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{
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SRU(LOW, DAI_PB01_I);
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SRU(LOW, DAI_PB02_I);
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SRU(LOW, DAI_PB03_I);
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SRU(LOW, DAI_PB04_I);
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SRU(LOW, DAI_PB05_I);
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SRU(LOW, DAI_PB06_I);
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SRU(LOW, DAI_PB07_I);
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SRU(LOW, DAI_PB08_I);
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SRU(LOW, DAI_PB09_I);
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SRU(LOW, DAI_PB10_I);
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SRU(LOW, DAI_PB11_I);
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SRU(LOW, DAI_PB12_I);
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SRU(LOW, DAI_PB13_I);
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SRU(LOW, DAI_PB14_I);
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SRU(LOW, DAI_PB15_I);
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SRU(LOW, DAI_PB16_I);
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SRU(LOW, DAI_PB17_I);
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SRU(LOW, DAI_PB18_I);
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SRU(LOW, DAI_PB19_I);
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SRU(LOW, DAI_PB20_I);
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//------------------------------------------------------------------------
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// Tie the pin buffer enable inputs LOW for all DAI pins so
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// that they are always input pins. This is GROUP F.
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SRU(LOW, PBEN01_I);
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SRU(LOW, PBEN02_I);
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SRU(LOW, PBEN03_I);
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SRU(LOW, PBEN04_I);
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SRU(LOW, PBEN05_I);
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SRU(LOW, PBEN06_I);
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SRU(LOW, PBEN07_I);
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SRU(LOW, PBEN08_I);
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SRU(LOW, PBEN09_I);
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SRU(LOW, PBEN10_I);
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SRU(LOW, PBEN11_I);
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SRU(LOW, PBEN12_I);
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SRU(LOW, PBEN13_I);
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SRU(LOW, PBEN14_I);
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SRU(LOW, PBEN15_I);
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SRU(LOW, PBEN16_I);
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SRU(LOW, PBEN17_I);
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SRU(LOW, PBEN18_I);
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SRU(LOW, PBEN19_I);
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SRU(LOW, PBEN20_I);
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}
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