/*
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* PLL.c
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*
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* Created on: 2022Äê3ÔÂ23ÈÕ
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* Author: graydon
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*/
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#include <def21489.h>
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#include <cdef21489.h>
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/*
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** The following definition is a good programming practice to follow,
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** in order to prevent the compiler from optimizing out any instructions
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** that it may think are non-essential.
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** It also makes code MISRA rule 2.1 compliant.
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*/
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#define NOP asm volatile("nop;")
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void initPLL_SDRAM()
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{
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int i, pmctlsetting;
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// Set INDIV bit in PMCTL register
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pmctlsetting = *pPMCTL;
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pmctlsetting |= INDIV;
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*pPMCTL= pmctlsetting;
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// Program PLL multiplier to same value as CLK_CFGx pins/previously programmed value in software
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*pPMCTL = pmctlsetting;
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// then place PLL in bypass mode
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pmctlsetting |= PLLBP;
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*pPMCTL = pmctlsetting;
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//Wait for recommended number of cycles
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for (i=0; i<4096; i++)
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NOP;
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// Bring PLL out of bypass mode by clearing PLLBP bit
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*pPMCTL ^= PLLBP;
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for (i=0; i<16; i++)
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NOP;
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pmctlsetting = *pPMCTL;
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// Clear the previous PLL multiplier
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pmctlsetting &= ~PLLM63;
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// Clear the INDIV bit
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pmctlsetting &= ~INDIV;
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// or set the INDIV bit
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// *pMCTL |= INDIV;
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*pPMCTL= pmctlsetting;
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// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
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// Fcclk = (CLKIN * 2 * M) / (N * D)
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// VCO frequency = 2*fINPUT*PLLM = 2*25*16 = 800 <= fVCOmax (800 MHz)
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// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1
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pmctlsetting= PLLM18|PLLD2|SDCKR2_5|DIVEN;
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*pPMCTL= pmctlsetting;
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pmctlsetting|= PLLBP; //Setting the Bypass bit
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pmctlsetting^= DIVEN; //Clearing the DIVEN bit
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*pPMCTL= pmctlsetting; // Putting the PLL into bypass mode
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//Wait for around 4096 cycles for the pll to lock.
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for (i=0; i<5000; i++)
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NOP;
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pmctlsetting = *pPMCTL;
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pmctlsetting ^= PLLBP; //Clear Bypass Mode
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*pPMCTL = pmctlsetting;
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//Wait for around 15 cycles for the output dividers to stabilize.
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for (i=0; i<16; i++)
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NOP;
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// InitSDRAM:
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// SDRAM memory on EZ-Board - MT48LC16M16A2-6A
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// 5.4ns @ CL = 3 ,167 MHz speed
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// Parameters
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// Config - 64M x 16(16M x 16 x 4)
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// Speed - 167 MHz
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// CAS Latency - 3
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// Row addressing - 8K(A0-A12)
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// Column addressing - 512(A0-A8)
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// No of Banks - 4
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//tRAS - 42ns
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//tRCD - 18ns
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//tRP - 18ns
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//tRC - 60ns( tRP + tRAS >= tRC)
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//tWR - (1CLK + 6ns)
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//For the 160 MHz case, tSDCLK = 1/160 MHz = 6.25ns
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// CAS Latency = 3
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// tRCD = 18 / 6.25 = 3(2.88)
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// tRP = 18 / 6.25 = 3(2.88)
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// tRC = 60 / 6.25 = 10
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// tRAS = 42/ 6.25 = 7(6.72)
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// tWR = (6.25 + 6)/6.25 = 2(1.96)
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// fSDCLK = 160 MHz
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// tREF= 64ms
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// NRA = 8192
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// RDIV = ((f SDCLK X t REF)/NRA) - (t RAS + t RP)
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// RDIV = (((160 X 10^6 x 64 x 10^-3)/8192) - (7 + 3))
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// RDIV = 1240 = 0x4D8
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#if 0
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*pSYSCTL |= MSEN; // Enables FLAG2 and 3 (IRQ2 and TIMEXP) as MS2 and 3
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// Mapping Bank 0 to SDRAM
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*pEPCTL |=B0SD;
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*pEPCTL &= ~(B1SD|B2SD|B3SD);
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//Programming the SDCTL register
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*pSDCTL= SDCL3|SDPSS|SDCAW9|SDRAW13|SDTRAS7|SDTRP3|SDTWR2|SDTRCD3|X16DE;
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// Change this value to optimize the performance for quazi-sequential accesses (step > 1)
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#define SDMODIFY 1 // Setting the Modify to 1
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*pSDRRC= (0x4D8)|(SDMODIFY<<17)|SDROPT;
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//*pSDRRC = (0x373)|SDMODIFY|SDROPT;
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*pSYSCTL |= EPDATA32; // Data [31:0] pins are configured as data lines
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// Flash is connected on Bank 1
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// Programming maximum waitstates
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*pAMICTL1 = AMIEN | BW8 | WS31 ;
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// SRAM is connected on Bank 3
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// SRAM part used - IS61WV102416BLL
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// As per datasheet access time is 10 ns, 8ns
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// Programming waitstates = 4
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*pAMICTL3 = AMIEN | BW16 | WS4;
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#endif
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//REGISTER:
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// MODE1|=PEYEN;
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}
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